Drain-Source capacitance in Cadence

[manada]

Hello,

I'm trying to design an RF T/R switch based on:

Y. Jin, and C. Nguyen, ``Ultra-Compact High-Linearity High-Power Fully Integrated DC-20~GHz 0.18~$\mu$m CMOS T/R Switch," IEEE Transaction on Microwave Theory and Techniques, vol. 55, no. 1, pp. 30-36, Jan. 2007.

Part of the process described in this paper uses the total drain-source capacitance of the MOSFETs, so I ran a DC simulation, pulled up the DC operating points, and tried to find the total capacitance based on:



But when I do this, my capacitance results are no where near what they get (even though my other results are very similar). Is there another way to do this? Do the capacitances listed in the DC operating point print-out actually correspond to these capacitances?

Please help!

 

[dick_freebird]

Some RF PDKs use a pretty hokey core FET model and
supplement it with a subcircuit "wrapper" that contains
most of the parasitics (FET compact models lacking L
entirely, and their behavior of C vs terminal voltages
may not fit the way you'd like). You should burrow into
the model chain and read the model statements to get
an idea about structure.

A MOS RF switch will have the gate connected only to
a very high value resistor. So the Cds may appear as
the sum of fringing D-S capacitance plus the series
Cdg*Cgs/(Cdg+Cgs) since the gate has nowhere else
to go.

Then, consider that they may have omitted some
details like finger count, total W or whatever if this
was anything like a commercial product with IP to
protect.