doubts regarding vhdl coding

[M.Shobana]

hi....
i want to know the basic requirements which need to do coding for finite state machine in vhdl.And i want to know how its output will be displayed while simulation.plz reply me quickly if anybdy knws

 

[treqer]

as in the coding on any platform.

Do not leave unused states.
remember that the wrong list of the sensitivity of the process in a simulation affects the output...

 

[TrickyDicky]

Minimum requirements: A text editor
to display it in simulation: you need a simulator, like modelsim.

 

[M.Shobana]

k sir....but i need to know about the procedure for coding finite state machine in vhdl.i dont have much knwledge abt tis.plz help me

 

[TrickyDicky]

try wikipedia: Finite-state machine - Wikipedia, the free encyclopedia
try google :VHDL Tutorial: Learn by Example

When you are then stuck on a more specific question (after you've written some code), come back and ask for more help.