doubts regarding Finite state machine coding

[M.Shobana]

hi.......
process(ps_state,x)
begin
case state is
when s1=>
if(x(1)==0) then
nextstate<=s2;
q1<="001";
else
nextstate<=sin;
q1<={q0,"000"};
end if;
case state is
when s2=>
if(x(2)==0) then
nextstate<=s3;
q2<="010";
else
nextstate<=sin;
q2<={q1,"000"};
end if;
end case;
end process;
z<=q1 & q2;
in this program we may have the size of q as either 3 0r 6 bits. z is an output bit;q1 and q2 are the intermediate outputs we have to show the intermediate result also.like q1 and q2 i have to detect up to q15 and finally we have to concatenate all the 15 values of q1,q2,.......q15 in z;size of the z will be vary based on the size of the q then how we can initialize the size of q and z?

if anybody knows solution for the above problem means please reply me quickly

 

[TrickyDicky]

there are multiple errors in your code.

q2 <= {q1, "000"}; is not valid VHDL.
state is missing from the sensitivity list.
== has no meaning in VHDL.

I first suggest you read through a VHDL tutorial.

secondly, the size of Z will never vary, it will always be fixed, as will the size of Q.