inputs to auVerilogToCell.....
1. library name...(given by us..)
2.location of netlist file..
3. name of the out put cell to be created..(given by us..)
4. location of the tech file...(is this has to be .tf format only or lef would be ok....or we have to convert .lef to .tf...?
5. location of ref libraries...(how do we convert lib files to gds...)
6. association betwn power/gnd nets...
4 point. no tf files and lef files are different. i have answered for ur previous question
h**p://
u need tf file for data preparation u can get it with std cell library.
5. lib file contains timing information of that paarticular block. it does not contain any physical information. u can use lef file which contains physical information instead of gds. But left has only physical dimensions of that block on internal circuits. its just like black box.