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Doubt:UART in full duplex mode

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Member level 3
Jan 20, 2005
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My doubt:

2 uarts communicating in full duplex mode (means both uart transmit & receive at same time).

Now my question is -
I am configuring 1st uart's baud rate 9600 and 2nd uart's 115200.
Is full duplex mode is possible in such case?

Thanks in Adv.


You have to check at datasheet.
UARTs of each uControlers have particular features.


Hi Andre,

Its not for uc, its my doubt.

What im thinking that how Processors-n-uart at both end will handle data transfer at 2 different baud rate? n that is in full duplex...i mean in design prospects.


UART's communicating with each other always need the same baud rate word size and number of stop and parity bits the same otherwise it will not work.

So full duplex is correct both TX and RX work at the same time. But its possible that from UART 1 TX is working at 115200 and RX is working at 9600 UART 2 will have RX working at 115200 and TX at 9600. Some UART's support this kind of operation but most chips do not support it. Only Z85C30 from ZILOG is supporting this to my knowledge but NOT UARTS on PC's or UART's in microcontrollers !. They always work at the same TX and RX speed although it's not needed by the standard.

Okay...Thanks Paul, thanks andre for sharing your ideas n info.....

I have few more doubts. Assume simple RS 232 UART.

1. In UART protocol, in each frame we have start bit, data, parity & stop bit.
What ever(in size) data may be, but it is divided into frame & txed or rxed.
Now here my ques is - why should i go for all that framing structure?? Just put first start bit & put all the data which is to be transmitted & at the end put stop bit, thats enough. But why we are going for framing structure as mentioned above?
(I know that is UART protocol is all about, but can we do like that?)

(What i can say is - At receiver side which is operating at same freq but Asynchronously, will miss its clock synchronization, thats why we are going for framing structure. )


Hi, Not a good idea to send ONE start bit 100 data bits and than ONE stop bit. The reason is very simple. We do framing of 8 bits and long streams of data are packed in a FRAME to make sure you know what, what is in the FRAME. So header, length and data and maybe even CRC. The Start bit makes the use of sync clock not needed since we resync every byte on the edge of the start bit. This is also the reason why we can't simply use ONE start bit and 100 data bits followed by a parity (or not) and a stop bit.

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