# doubt supply-independent biasing

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#### ffsher100

##### Junior Member level 3
i got a question from Razavi textbook in chapter 11.2 : Supply-Independent Biasing
===><figure 1>
===><figure 2>
by figure2, it looks like vdd really has no effect on the figure 1 CKT.

the textbook also introduce start-up circuit M5 into the design as following:
===><figure 3>
when simulating the circuit with startup(M5), it seem to be effected by VDD.
Current Iout, Iref vary with VDD.
In practice, figure 3 become Supply-dependent Biasing since startup must include.
how could this be? if using figure 3, supply- independent case never happen.

below figure, i sweep .dc vdd.

As you see vdd ramp from 0v to 5v, current Iref and Iout are not constant if vdd>2.8v

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#### leo_o2

Actually, start-up circuit in Fig.3 is poor.
Pls change to other start-up circuit like detecting mode.

#### ffsher100

##### Junior Member level 3
Pls change to other start-up circuit like detecting mode.

Hi leo_o2, could you provide any detecting mode startup circuit for reference?

#### leo_o2

Use a current mirror to copy the bias current and compare it with a current generated by a resistor to create start-up signal. When bias current is big enough, the start-up current will be turned off completely.

#### ffsher100

##### Junior Member level 3
Hi leo_o2,

here, my original question is that the Vgs1,Iref,Iout...ect, in Figure 1 should not be affected by Vdd vary.
or my understand is wrong.
In above the fourth figure show current Iout, Iref vary with VDD.
I confuse....

#### dick_freebird

Think "supply independent over -some range of VDD-".
Not zero to breakdown, not even close. Just good
enough for the job (+/-__% for +/-10% VDD, like).

Startup conditions may not have the same accuracy
requirement as within-supply-spec-range, just function.
That's for you to determine, not assume. Unless you
like extra difficulty.

#### leo_o2

If you use the start-up circuit I recommended, Iref will not vary with VDD.

Hi leo_o2,

here, my original question is that the Vgs1,Iref,Iout...ect, in Figure 1 should not be affected by Vdd vary.
or my understand is wrong.
In above the fourth figure show current Iout, Iref vary with VDD.
I confuse....

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