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Doubt Regarding Verilog Code

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Yukta2007

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My group is having a project to be implemented on PUF(Physical unclonable functions) using Verilog. Having written the code in Verilog we are facing an error which we could not rectify even after several tries. It would be really helpful if you would help us rectify this error. And the error which we get after compilation is " ** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/ring3.v(100): near "always": syntax error, unexpected always, expecting class. " Please help.

The code for PUF is given below. I have marked the error line in red.
Code: 
module oscillator(input enable,output wave);
nand g1(n0,enable,n74);
not b1(n1,n0);
not b2(n2,n1);
not b3(n3,n2);
not b4(n4,n3);
not b5(n5,n4);
not b6(n6,n5);
not b7(n7,n6);
not b8(n8,n7);
not b9(n9,n8);
not b10(n10,n9);
not b11(n11,n10);
not b12(n12,n11);
not b13(n13,n12);
not b14(n14,n13);
not b15(n15,n14);
not b16(n16,n15);
not b17(n17,n16);
not b18(n18,n17);
not b19(n19,n18);
not b20(n20,n19);
not b21(n21,n20);
not b22(n22,n21);
not b23(n23,n22);
not b24(n24,n23);
not b25(n25,n24);
not b26(n26,n25);
not b27(n27,n26);
not b28(n28,n27);
not b29(n29,n28);
not b30(n30,n29);
not b31(n31,n30);
not b32(n32,n31);
not b33(n33,n32);
not b34(n34,n33);
not b35(n35,n34);
not b36(n36,n35);
not b37(n37,n36);
not b38(n38,n37);
not b39(n39,n38);
not b40(n40,n39);
not b41(n41,n40);
not b42(n42,n41);
not b43(n43,n42);
not b44(n44,n43);
not b45(n45,n44);
not b46(n46,n45);
not b47(n47,n46);
not b48(n48,n47);
not b49(n49,n48);
not b50(n50,n49);
not b51(n51,n50);
not b52(n52,n51);
not b53(n53,n52);
not b54(n54,n53);
not b55(n55,n54);
not b56(n56,n55);
not b57(n57,n56);
not b58(n58,n57);
not b59(n59,n58);
not b60(n60,n59);
not b61(n61,n60);
not b62(n62,n61);
not b63(n63,n62);
not b64(n64,n63);
not b65(n65,n64);
not b66(n66,n65);
not b67(n67,n66);
not b68(n68,n67);
not b69(n69,n68);
not b70(n70,n69);
not b71(n71,n70);
not b72(n72,n71);
not b73(n73,n72);
not b74(n74,n73);
not bf(wave,n74);

endmodule

module mux4(input d0,input d1,input d2,input d3,input s0,input s1,output M);
wire s1_n, s0_n, t0,t1,t2,t3;

not n0(s0_n,s0);
not n1(s1_n,s1);
and g0(t0,s0_n,s1_n,d0);
and g1(t1,s0,s1_n,d1);
and g2(t2,s0_n,s1,d2);
and g3(t3,s0,s1,d3);
or g4(M,t0,t1,t2,t3);
endmodule


module mux16(input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, input d8, input d9, input d10, input d11, input d12, input d13, input d14, input d15, input s0, input s1, input s2, input s3, output M);

wire t0,t1,t2,t3;

mux4 m0(.d0(d0), .d1(d1), .d2(d2), .d3(d3), .s1(s1), .s0(s0), .M(t0));
mux4 m1(.d0(d4), .d1(d5), .d2(d6), .d3(d7), .s1(s1), .s0(s0), .M(t1));
mux4 m2(.d0(d8), .d1(d9), .d2(d10), .d3(d11), .s1(s1), .s0(s0), .M(t2));
mux4 m3(.d0(d12), .d1(d13), .d2(d14), .d3(d15), .s1(s1), .s0(s0), .M(t3));
mux4 m4(.d0(t0), .d1(t1), .d2(t2), .d3(t3), .s1(s3), .s0(s2), .M(M));
endmodule


always @(posedge enable)

begin
Ch0 = challenge;
Ch1[7] = challenge[5];
Ch1[6] = challenge[6];
Ch1[5] = challenge[7];
Ch1[4] = challenge[4];
Ch1[3] = challenge[1];
Ch1[2] = challenge[0];
Ch1[1] = challenge[3];
Ch1[0] = challenge[2];

Ch2[7] = challenge[6];
Ch2[6] = challenge[5];
Ch2[5] = challenge[4];
Ch2[4] = challenge[7];
Ch2[3] = challenge[2];
Ch2[2] = challenge[1];
Ch2[1] = challenge[3];
Ch2[0] = challenge[0];

end


// Direct the result to the output

(* KEEP *) FDC cont0(.D(1), .C(done), .CLR(~enable), .Q(resClk[0]));
(* KEEP *) FDC cont1(.D(resClk[0]), .C(done), .CLR(~enable), .Q(resClk[1]));
(* KEEP *) FDC cont2(.D(resClk[1]), .C(done), .CLR(~enable), .Q(resClk[2]));
(* KEEP *) FDC cont3(.D(resClk[2]), .C(done), .CLR(~enable), .Q(resClk[3]));
(* KEEP *) FDC cont4(.D(resClk[3]), .C(done), .CLR(~enable), .Q(resClk[4]));
(* KEEP *) FDC cont5(.D(resClk[4]), .C(done), .CLR(~enable), .Q(resClk[5]));
(* KEEP *) FDC cont6(.D(resClk[5]), .C(done), .CLR(~enable), .Q(resClk[6]));
(* KEEP *) FDC cont7(.D(resClk[6]), .C(done), .CLR(~enable), .Q(resClk[7]));

// Flip Flops to store the outputs

(* KEEP *) FDC res0(.D(res), .C(resClk[0]), .CLR(~enable), .Q(resTemp[0]));
(* KEEP *) FDC res1(.D(res), .C(resClk[1]), .CLR(~enable), .Q(resTemp[1]));
(* KEEP *) FDC res2(.D(res), .C(resClk[2]), .CLR(~enable), .Q(resTemp[2]));
(* KEEP *) FDC res3(.D(res), .C(resClk[3]), .CLR(~enable), .Q(resTemp[3]));
(* KEEP *) FDC res4(.D(res), .C(resClk[4]), .CLR(~enable), .Q(resTemp[4]));
(* KEEP *) FDC res5(.D(res), .C(resClk[5]), .CLR(~enable), .Q(resTemp[5]));
(* KEEP *) FDC res6(.D(res), .C(resClk[6]), .CLR(~enable), .Q(resTemp[6]));
(* KEEP *) FDC res7(.D(res), .C(resClk[7]), .CLR(~enable), .Q(resTemp[7]));

// Control

always (@resClk) // Use this signal to change the states

begin
case (resClk)

8’b00000000: begin
select = Ch0;
// next = 1;
// #5
// next = 0;
end

8’b00000001: begin
select = Ch1;
// next = 1;
// #5
// next = 0;
end

8’b00000011: begin
select = Ch2;
// next = 1;
// #5
// next = 0;
end

8’b00000111: begin
select = Ch3;
// next = 1;
// #5
// next = 0;
end

8’b00001111: begin
select = Ch4;
// next = 1;
// #5
// next = 0;
end

8’b00011111: begin
select = Ch5;
// next = 1;
// #5
// next = 0;
end

8’b00111111: begin
select = Ch6;
// next = 1;
// #5
// next = 0;
end

8’b01111111: begin
select = Ch7;
// next = 1;
// #5
// next = 0;
end

endcase

module puf( challenge, response, enable, ready
);

input [7:0] challenge;
input enable;
output [7:0] response;
output ready;

// Control signals
reg [7:0] select;
wire CE; // Control the counters
wire FCE; // Control final register load
wire done; // Signal that we obtained a result and stop the counters
reg next = 0; // Reserved to clear a flip flop for ’done’

// Use challenge to select MUXes outputs
mux16 m0(.d0(w[0]), .d1(w[1]), .d2(w[2]), .d3(w[3]), .d4(w[4]), .d5(w[5]), .d6(w[6]), .d7(w[7]),
.d8(w[8]), .d9(w[9]), .d10(w[10]), .d11(w[11]), .d12(w[12]), .d13(w[13]), .d14(w[14]), .d15(w[15]),
.s3(select[3]), .s2(select[2]), .s1(select[1]), .s0(select[0]), .M(C0));

mux16 m1(.d0(w[0]), .d1(w[2]), .d2(w[1]), .d3(w[12]), .d4(w[7]), .d5(w[5]), .d6(w[4]), .d7(w[6]),
.d8(w[9]), .d9(w[14]), .d10(w[8]), .d11(w[15]), .d12(w[3]), .d13(w[13]), .d14(w[10]), .d15(w[11]),
.s3(select[7]), .s2(select[6]), .s1(select[5]), .s0(select[4]), .M(C1));
 
Last edited by a moderator:

It would help to point out line 100 in a comment, but I assume that is the always following the endmodule keyword. There are 2 always block that are not inside any module.
 

dave_59 said:
It would help to point out line 100 in a comment, but I assume that is the always following the endmodule keyword. There are 2 always block that are not inside any module.
Click to expand...
Could you please put the corrected code? It would be of immense help. Thanks in advance
 

I'd say just inspecting the code that everything between the first always and the endcase was supposed to be inside the puf module
 

ads-ee said:
I'd say just inspecting the code that everything between the first always and the endcase was supposed to be inside the puf module
Click to expand...

I made the changes according to what you said but it is still generating a lot of errors in the declaration of module "puf". If possible, could you put the corrected code here? It would be very helpful.
Thank you

Code: 
module oscillator(input enable,output wave);

nand g1(n0,enable,n74);
not b1(n1,n0);
not b2(n2,n1);
not b3(n3,n2);
not b4(n4,n3);
not b5(n5,n4);
not b6(n6,n5);
not b7(n7,n6);
not b8(n8,n7);
not b9(n9,n8);
not b10(n10,n9);
not b11(n11,n10);
not b12(n12,n11);
not b13(n13,n12);
not b14(n14,n13);
not b15(n15,n14);
not b16(n16,n15);
not b17(n17,n16);
not b18(n18,n17);
not b19(n19,n18);
not b20(n20,n19);
not b21(n21,n20);
not b22(n22,n21);
not b23(n23,n22);
not b24(n24,n23);
not b25(n25,n24);
not b26(n26,n25);
not b27(n27,n26);
not b28(n28,n27);
not b29(n29,n28);
not b30(n30,n29);
not b31(n31,n30);
not b32(n32,n31);
not b33(n33,n32);
not b34(n34,n33);
not b35(n35,n34);
not b36(n36,n35);
not b37(n37,n36);
not b38(n38,n37);
not b39(n39,n38);
not b40(n40,n39);
not b41(n41,n40);
not b42(n42,n41);
not b43(n43,n42);
not b44(n44,n43);
not b45(n45,n44);
not b46(n46,n45);
not b47(n47,n46);
not b48(n48,n47);
not b49(n49,n48);
not b50(n50,n49);
not b51(n51,n50);
not b52(n52,n51);
not b53(n53,n52);
not b54(n54,n53);
not b55(n55,n54);
not b56(n56,n55);
not b57(n57,n56);
not b58(n58,n57);
not b59(n59,n58);
not b60(n60,n59);
not b61(n61,n60);
not b62(n62,n61);
not b63(n63,n62);
not b64(n64,n63);
not b65(n65,n64);
not b66(n66,n65);
not b67(n67,n66);
not b68(n68,n67);
not b69(n69,n68);
not b70(n70,n69);
not b71(n71,n70);
not b72(n72,n71);
not b73(n73,n72);
not b74(n74,n73);
not bf(wave,n74);
endmodule

module mux4(input d0,input d1,input d2,input d3,input s0,input s1,output M);

wire s1_n, s0_n, t0,t1,t2,t3;
not n0(s0_n,s0);
not n1(s1_n,s1);
and g0(t0,s0_n,s1_n,d0);
and g1(t1,s0,s1_n,d1);
and g2(t2,s0_n,s1,d2);
and g3(t3,s0,s1,d3);
or g4(M,t0,t1,t2,t3);

endmodule


module mux16(input d0, input d1, input d2, input d3, input d4, input d5, input d6, input d7, input d8, input d9, input d10, input d11, input d12, input d13, input d14, input d15, input s0, input s1, input s2, input s3, output M);

wire t0,t1,t2,t3;
mux4 m0(.d0(d0), .d1(d1), .d2(d2), .d3(d3), .s1(s1), .s0(s0), .M(t0));
mux4 m1(.d0(d4), .d1(d5), .d2(d6), .d3(d7), .s1(s1), .s0(s0), .M(t1));
mux4 m2(.d0(d8), .d1(d9), .d2(d10), .d3(d11), .s1(s1), .s0(s0), .M(t2));
mux4 m3(.d0(d12), .d1(d13), .d2(d14), .d3(d15), .s1(s1), .s0(s0), .M(t3));
mux4 m4(.d0(t0), .d1(t1), .d2(t2), .d3(t3), .s1(s3), .s0(s2), .M(M));
endmodule 

module puf(input wire [15:0] w, input challenge, input wire [7:0] Ch1, input wire [7:0] Ch2, input enable, input Ch0, input Ch3, input Ch4, input Ch5, input Ch6, input Ch7, input resClk, input resTemp, output [7:0] response, output ready);

output ready;

// Control signals

reg [7:0] select;

wire CE; // Control the counters

wire FCE; // Control final register load

wire done; // Signal that we obtained a result and stop the counters

reg next = 0; // Reserved to clear a flip flop for ?done?

// Use challenge to select MUXes outputs

always @ (posedge enable)

begin

Ch0 = challenge;

Ch1[7] = challenge[5];

Ch1[6] = challenge[6];

Ch1[5] = challenge[7];

Ch1[4] = challenge[4];

Ch1[3] = challenge[1];

Ch1[2] = challenge[0];

Ch1[1] = challenge[3];

Ch1[0] = challenge[2];

Ch2[7] = challenge[6];

Ch2[6] = challenge[5];

Ch2[5] = challenge[4];

Ch2[4] = challenge[7];

Ch2[3] = challenge[2];

Ch2[2] = challenge[1];

Ch2[1] = challenge[3];

Ch2[0] = challenge[0];

end

// Direct the result to the output

(* KEEP *) FDC cont0(.D(1), .C(done), .CLR(~enable), .Q(resClk[0]));

(* KEEP *) FDC cont1(.D(resClk[0]), .C(done), .CLR(~enable), .Q(resClk[1]));

(* KEEP *) FDC cont2(.D(resClk[1]), .C(done), .CLR(~enable), .Q(resClk[2]));

(* KEEP *) FDC cont3(.D(resClk[2]), .C(done), .CLR(~enable), .Q(resClk[3]));

(* KEEP *) FDC cont4(.D(resClk[3]), .C(done), .CLR(~enable), .Q(resClk[4]));

(* KEEP *) FDC cont5(.D(resClk[4]), .C(done), .CLR(~enable), .Q(resClk[5]));

(* KEEP *) FDC cont6(.D(resClk[5]), .C(done), .CLR(~enable), .Q(resClk[6]));

(* KEEP *) FDC cont7(.D(resClk[6]), .C(done), .CLR(~enable), .Q(resClk[7]));

// Flip Flops to store the outputs

(* KEEP *) FDC res0(.D(res), .C(resClk[0]), .CLR(~enable), .Q(resTemp[0]));

(* KEEP *) FDC res1(.D(res), .C(resClk[1]), .CLR(~enable), .Q(resTemp[1]));

(* KEEP *) FDC res2(.D(res), .C(resClk[2]), .CLR(~enable), .Q(resTemp[2]));

(* KEEP *) FDC res3(.D(res), .C(resClk[3]), .CLR(~enable), .Q(resTemp[3]));

(* KEEP *) FDC res4(.D(res), .C(resClk[4]), .CLR(~enable), .Q(resTemp[4]));

(* KEEP *) FDC res5(.D(res), .C(resClk[5]), .CLR(~enable), .Q(resTemp[5]));

(* KEEP *) FDC res6(.D(res), .C(resClk[6]), .CLR(~enable), .Q(resTemp[6]));

(* KEEP *) FDC res7(.D(res), .C(resClk[7]), .CLR(~enable), .Q(resTemp[7]));

// Control

always @ (resClk) // Use this signal to change the states

case (resClk)

8'b00000000: begin

select = Ch0;

// next = 1;

// #5

// next = 0;

end

8'b00000001: begin

select = Ch1;

// next = 1;

// #5

// next = 0;

end

8'b00000011: begin

select = Ch2;

// next = 1;

// #5

// next = 0;

end

8'b00000111: begin

select = Ch3;

// next = 1;

// #5

// next = 0;

end

8'b00001111: begin

select = Ch4;

// next = 1;

// #5

// next = 0;

end

8'b00011111: begin

select = Ch5;

// next = 1;

// #5

// next = 0;

end

8'b00111111: begin

select = Ch6;

// next = 1;

// #5

// next = 0;

end

8'b01111111: begin

select = Ch7;

// next = 1;

// #5

// next = 0;

end

endcase

mux16 m0(.d0(w[0]), .d1(w[1]), .d2(w[2]), .d3(w[3]), .d4(w[4]), .d5(w[5]), .d6(w[6]), .d7(w[7]),

.d8(w[8]), .d9(w[9]), .d10(w[10]), .d11(w[11]), .d12(w[12]), .d13(w[13]), .d14(w[14]), .d15(w[15]),

.s3(select[3]), .s2(select[2]), .s1(select[1]), .s0(select[0]), .M(C0));

mux16 m1(.d0(w[0]), .d1(w[2]), .d2(w[1]), .d3(w[12]), .d4(w[7]), .d5(w[5]), .d6(w[4]), .d7(w[6]),

.d8(w[9]), .d9(w[14]), .d10(w[8]), .d11(w[15]), .d12(w[3]), .d13(w[13]), .d14(w[10]), .d15(w[11]),

.s3(select[7]), .s2(select[6]), .s1(select[5]), .s0(select[4]), .M(C1));

endmodule
 
Last edited by a moderator:

@Yukta2007 ,
What is stopping you from makign changes to the RTL, simulating the code, if errors persists, fixing the related parts and re-simulating your code?
A simulator and test-bench exists to debug such stuff!

Do you not understand the error messages shown by the simulator or are you clueless how to fix the RTL?
 

dpaul said:
@Yukta2007 ,
What is stopping you from makign changes to the RTL, simulating the code, if errors persists, fixing the related parts and re-simulating your code?
A simulator and test-bench exists to debug such stuff!

Do you not understand the error messages shown by the simulator or are you clueless how to fix the RTL?
Click to expand...
I am unable to fix the RTL. Could you please help?
 

Yukta2007 said:
I am unable to fix the RTL. Could you please help?
Click to expand...
We are not here to do your work for you. If we did then you wouldn't deserve the grade/pay you get for doing this project.

If you have an error that shows up then tell us the tool that produces the error and cut and paste the error that is generated by that tool into a code window on the forum.

Also make it easier for us to help you by submitting your code using syntax=verilog & /syntax tags instead (close ] & open [ brackets removed to avoid tags taking effect). If you use the syntax tags the line numbers will show up on the code. Also if you have multiple files put the code for each file inside the syntax tags separately instead of one giant "file".

FYI nobody writes code like this using Verilog gate primitives. Code like this is a maintenance nightmare.
 
Was this Verilog code generated by some high level synthesis tool? It seems like generated by an algorithm.
 

niciki said:
Was this Verilog code generated by some high level synthesis tool? It seems like generated by an algorithm.
Click to expand...
We generated it on Model Sim but we have one error. Could you please help us with that?
--- Updated ---

1610370378074.png



Something is wrong with the "always" part. Please help.
 
Last edited:

You were already told why you have a problem with the always statement outside a module back in post #2. And post #3 says where the always code probably needs to reside based on the signal names in the block.

Are you even paying attention to the replies you are receiving?

If you don't know always blocks need to be inside modules then you don't know enough Verilog to even start writing code. You need to read a basic tutorial on Verilog.
 

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