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Doubt regarding using ODIN II tool for converting a verilog file into BLIF format

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prem_1101

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I am an M.tech student and have been working on a project related to FPGA architecture research.In this, among other things i am supposed to convert verilog files into BLIF format as a part of technology mapping.While some files are getting neatly converted,some files do not.I dont understand why. B'cuz the files which are not getting converted too are functionally correct and do get compiled in MODELSIM. Please get back to me on this as its really urgent
 

FvM

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I can just guess that your Verilog describes nonsynthesizable hardware. An example would help.
 

Mohammed_Verification

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Hi,
Kindly note that all verilog code (i.e. get compiled using simulation tools) can not be synthesized. In other word you have developed the RTL code not the synthesizable code.

See, all synthesizable code must be a RTL code but every RTL code may or may not be a synthesizable code.
Moreover, as per my knowledge ODIN II is an HLS tools, before doing this you should have the knowledge of praser, eloborator and optimizer which is the fundamental part of an compiler in HLS tool.

Hope it may be helpful.
 

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