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doubt regarding illegeal referrence to net

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srinpraveen

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This is my code for a priority arbiter of an ahb bus. I am new to verilog. I get some errors as below.

** Error: D:/arbiter.v(116): (vlog-2110) Illegal reference to net "hresp".
** Error: D:/arbiter.v(123): (vlog-2110) Illegal reference to net "hsplitx".
** Error: D:/arbiter.v(157): (vlog-2110) Illegal reference to net "hresp".
** Error: D:/arbiter.v(164): (vlog-2110) Illegal reference to net "hsplitx".
** Error: D:/arbiter.v(199): (vlog-2110) Illegal reference to net "hresp".
** Error: D:/arbiter.v(206): (vlog-2110) Illegal reference to net "hsplitx".
** Error: D:/arbiter.v(234): (vlog-2110) Illegal reference to net "hresp".
** Error: D:/arbiter.v(241): (vlog-2110) Illegal reference to net "hsplitx".

The code is here. Kindly point out why these errors are occurring. I understand that wires cannot be assigned values inside always block. But I don't really understand how to modify this code to remove the error. If someone could modify this, I would be grateful. Here is the code.

module arbiter(req0, req1, req2, req3, hsplitx, htrans, hburst, hresp, hready, hclk, hresetn, gnt0, gnt1, gnt2, gnt3, hmaster);
input req0;
input req1;
input req2;
input req3;
input [1:0] hsplitx;
input htrans;
input hburst;
input hresp;
input hready;
input hclk;
input hresetn;
output reg gnt0;
output reg gnt1;
output reg gnt2;
output reg gnt3;
output [1:0] hmaster;
reg [1:0] hmaster;
reg [2:0] arbiter_state;
reg [1:0] sflag;
reg [3:0] count;

always @(posedge hclk or negedge hresetn)
begin
if (hresetn == 0)
begin
gnt0<=0;
gnt1<=0;
gnt2<=0;
gnt3<=0;
arbiter_state<=0;
end

else
case(arbiter_state)

0: //wait state
begin
if((hready==1) && (hresp==0) && (hburst==0))
begin
gnt0<=0;
gnt1<=0;
gnt2<=0;
gnt3<=0;
if(req0==1)
arbiter_state<=1;
else if(req1==1)
arbiter_state<=2;
else if(req2==1)
arbiter_state<=3;
else if(req3==1)
arbiter_state<=4;
else
arbiter_state <= arbiter_state;
end
else
arbiter_state<=arbiter_state;
end


1: //1st master (highest priority master and the default master)
begin
if((hready==1) && (hresp==0) && (hburst==0) && (sflag!=1))
begin
gnt0<=1;
hmaster<=1;
gnt1<=0;
gnt2<=0;
gnt3<=0;
if(req0==1)
arbiter_state<=1;
else if(req1==1)
arbiter_state<=2;
else if(req2==1)
arbiter_state<=3;
else if(req3==1)
arbiter_state<=4;
else
begin
if((htrans==0) && (count<=16))
begin
count<=count+1;
arbiter_state<=1;
end

else
begin
if(count==16)
begin
count<=0;
arbiter_state<=0;
end
else
arbiter_state<=1;
end
end
end

else if((hready==1) && (hresp==1) && (hburst==0) && (sflag==0))
begin
sflag<=1;
hresp<=0;
arbiter_state<=0;
end

else if((hready==1) && (hsplitx==1) && (sflag==1))
begin
gnt0<=1; hmaster<=1; gnt1<=0; gnt2<=0; gnt3<=0;
sflag<=0; hsplitx<=0;
arbiter_state<=1;
end

else
arbiter_state<=arbiter_state;
end



2: //2nd master (second priority)
begin
if((hready==1) && (hresp==0) && (hburst==0) && (sflag!=2))
begin
gnt0<=0;
gnt1<=1;
hmaster<=2;
gnt2<=0;
gnt3<=0;

if(req1==1)
arbiter_state<=2;
else if(req2==1)
arbiter_state<=3;
else if(req3==1)
arbiter_state<=4;
else
arbiter_state<=1;

end

else if((hready==1) && (hresp==1) && (hburst==0) && (sflag==0))
begin
sflag<=2;
hresp<=0;
arbiter_state<=0;
end

else if((hready==1) && (hsplitx==2) && (sflag==2))
begin
gnt0<=0; gnt1<=1; hmaster<=2; gnt2<=0; gnt3<=0;
sflag<=0; hsplitx<=0;
arbiter_state<=2;
end

else
arbiter_state<=arbiter_state;
end



3: //3rd master (third priority)
begin
if((hready==1) && (hresp==0) && (hburst==0) && (sflag!=3))
begin
gnt0<=0;
gnt1<=0;
gnt2<=1;
hmaster<=3;
gnt3<=0;

if(req2==1)
arbiter_state<=3;
else if(req0==1)
arbiter_state<=1;
else if(req1==1)
arbiter_state<=2;
else if(req3==1)
arbiter_state<=4;
else
arbiter_state<=1;
end

else if((hready==1) && (hresp==1) && (hburst==0) && (sflag==0))
begin
sflag<=3;
hresp<=0;
arbiter_state<=0;
end

else if((hready==1) && (hsplitx==3) && (sflag==3))
begin
gnt0<=0; gnt1<=0; gnt2<=1; hmaster<=3;gnt3<=0;
sflag<=0; hsplitx<=0;
arbiter_state<=3;
end

else
arbiter_state<=arbiter_state;
end


4: //4th master (fourth or last priority)
begin
if((hready==1) && (hresp==0) && (hburst==0) && (sflag!=4))
begin
gnt0<=0;
gnt1<=0;
gnt2<=0;
gnt3<=1;
hmaster<=4;

if(req3==1)
arbiter_state<=4;
else
arbiter_state<=1;
end

else if((hready==1) && (hresp==1) && (hburst==0) && (sflag==0))
begin
sflag<=4;
hresp<=0;
arbiter_state<=0;
end

else if((hready==1) && (hsplitx==4) && (sflag==4))
begin
gnt0<=0; gnt1<=0; gnt2<=0; gnt3<=1; hmaster<=4;
sflag<=0; hsplitx<=0;
arbiter_state<=4;
end

else
arbiter_state<=arbiter_state;
end

default: arbiter_state<=1;
endcase
end
endmodule

---------- Post added at 12:46 ---------- Previous post was at 12:31 ----------

I now realise maybe I am tampering too much with the input signals such as checking values, asserting and de-asserting the inputs. Do I need to store them in a reg or something before the always block? Also point out if there are any other blatant errors. Thanks.
 

Have you understood the concept of "input"?

Asserting and deasserting of inputs to a module cannot be done with in a module. Think logically whether it makes sense it to deassert with in a module

if you wanna input to be deasserted after certain condition, generate a control signal and make it as output and pass it on to the other module which is generating the input so that it will be deaseerted accordingly.
 

Thanks for pointing out my mistake. I will look into it and get back. I will store the inputs into registers inside the module and use the registers alone instead of tampering with the inputs and it makes perfect sense that we should not assert or deassert the inputs. Thanks again. I will get back after making amendments
 

Update:- I got the code to compile now. Thanks dcreddy. I am now storing my inputs into regs and then playing with the regs which are storing the inputs. No errors. Got to write a testbench now. Thanks and have a nice day.
 

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