Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

doubt regarding common mode swing

Status
Not open for further replies.

srinpraveen

Member level 2
Joined
Dec 2, 2009
Messages
48
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,731
Dear friends,
1) I am having some difficuty understanding why it is necessary to consider common mode input swing for a simple differential amplifier. I know that the common mode gain should be made less. Differential gain should be made high. And in other words, the Common mode signal rejection ratio should be high. But I don't understand why we need to consider the Vic input range. Let me remind that I am using Vic+Vid/2 and Vic-Vid/2 as the inputs to the diff pair. In this case, I read that as Vic increases, the diff pair transistor is thrown to cut off. But can someone explain in easier words? I don't understand the other threads also addressing similar topics.
Thanks for the understanding.

2) Also I have 1 more doubt. For a differential amplifier, we activate only the differential mode right? So all we are going to do is make Vic=0 ie. ground Vic so that only +Vid/2 gets applied to 1 MOS and -Vid/2 gets applied to other MOS. Is this right? So why do we need to bother about Vic value or Vic swing?

3) Also why are we sending the inputs as Vic+Vid/2 and Vic-Vid/2 we can just send just +Vid and -Vid right? Or maybe +Vid/2 and -Vid/2 Or V+dv and V-dv? Why have Vic unnecessarily?
 

LvW

Advanced Member level 5
Joined
May 7, 2008
Messages
5,858
Helped
1,746
Reputation
3,496
Reaction score
1,346
Trophy points
1,393
Location
Germany
Activity points
39,553
I think, all three questions can be answered as follows:

Consider the simplest case with Vin2=0 and Vin1=1V.
You always can split the difference Vin1-Vin2 into two voltages with two different gain values:
(a) a common mode voltage of (1+0)/2=0.5 volts (to be amplified with the common mode gain) and
(b) another voltage that can pe called "push-pull" voltage that is (1-0)/2=0.5volts (to be amplified with a gain that is much larger).

That means: Applying a pure differential signal at the input always results in one part that has common mode properties.
In the above example both parts are even equal.
But - luckily - the common mode voltage is amplified with a small gain value only.

The above is no surprise: If you have any two numbers (positive or negative) you always can find two other numbers x, y that (a) are common to both (mean value) or (b) have the value (x-y)/2 with different sign.
Example: x=+100 and y=-20. That means: a=40 and b=+/- 60 : Proof: 40+60=100 and 40-60=-20.

There is one exception that only has academical (and no practical) meaning: Vin1=-Vin2. Only in this case, the common mode part disappears.
Any further question?
 

srinpraveen

Member level 2
Joined
Dec 2, 2009
Messages
48
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,731
@LvW, Thanks. The explanation was excellent in clarifying the reason of existance of a common mode component in the input. Can you throw a few more points about how the common mode swing should be? What are its upper and lower limits of it? What will happen if the common mode swing is holding an "improper" value? I was reading that the diff pair MOS on the right hand side goes to non-linear region if Vic is increased too much. I didn't understand this point too convincingly. Can you clarify that statement?
 

LvW

Advanced Member level 5
Joined
May 7, 2008
Messages
5,858
Helped
1,746
Reputation
3,496
Reaction score
1,346
Trophy points
1,393
Location
Germany
Activity points
39,553
Hi srinpraveen,

the common mode range of diff. amps strongly depends on the respective topology of the input stage (resistors, current sources) as well as on the active devices (BJT, FET).
As a general answer, one can state that the specified common mode range gives limits that must not be exceeded in order to ensure normal (quasi-linear) operation of the input transistors. I suppose, you can imagine that there are certain upper and lower limits.
 

srinpraveen

Member level 2
Joined
Dec 2, 2009
Messages
48
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,731
@Lvw, Excellent...Thanks for the explanation. That helped.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top