Doubt in SAR ADC IEEE paper

[Chinmaye]

Hello all,

I am trying to understand the ieee paper "A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter" from the 1980s. I am unable to understand one circuit from it(Attached). The Sub ADC is a SAR ADC. All the capacitors used are unit capacitors, (Not binary weighted) and output taken is differential. How does it work as ADC?
Please help.

 

[D.A.(Tony)Stewart]

It appears to be what is called a Pipelined Redundant Signed Digit (RSD) error correction technique.

https://www.google.com/search?num=3...0....0...1..64.psy-ab..0.0.0....0.KGhBf6sMDjk