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Doubt in quartus synthesis attribute --- ramstyle--

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pranavam

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Hai ,

I have used the follwing code in my design..

(* ramstyle = "M4K" *) reg [0:7] my_ram[0:63]; in Verilog standard 2001..

The device i selected is cyclone II 2c20f484c7 .... And am using quartus II v6.0....

After complilation total memory bits used stick to zero bits....

plz help...
Do i need to change any other options in quartus to turn on this feature.... ?
 

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