Doubt in Functionality of DDR3

[carrot]

Hi,

Can anyone help me in understanding the below two sentences especially the second sentence:

The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at
the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four
clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.

Thanks

 

[useless_skew]

Memory controller can operate at a higher clock frequency. But DRAM core cells can operate only at limited frequency.
In single data rate SDRAM, the physical interface was acting at the same frequency as the DRAM memory cell and the IO.
But in case of DDR SDRAM, the data rate was doubled (DDR SDRAM physical interface sends and receives data at both the edges of clock) for the same "x" frequency. DRAM memory cell array also works at "x" frequency but can send and receive data only at a single clock edge.
Then how the data rate gets doubled? Ans - prefetch mechanism.

DDR SDRAM does a prefetch of 2n bit wide data.
Similarly, DDR2 SDRAM does a prefetch of 4n bit wide data and DDR3 8n bit wide data.

Without increasing the DRAM cell array frequency, we are able to achieve higher data rates due to pre-fetch mechanism.

 

[sree205]

So, is it safe to assume this scenario is correct ?

For a 'n' value of 8-bits or one byte, internal DRAM core cells fetches 64 bits or 8bytes of data in one go and
this data is transferred at the I/O in 4 clock cycles by sending 1 byte at each edge of the clock, be it +ve or -ve edge
of the clock and an overall data rate of 8 bytes?

If this is the case, then the I/O clock frequency should be 4 times that of the internal DRAM clock frequency as well, right ?

 

[useless_skew]

Yes. You are right...