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Doubt in Design compiler

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vsrpkumar

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I am novice to design compiler

This is statement in design compiler
Ideal network propagation can traverse combinational cells, but it stops at sequential cells, even if the sequential cells are connected to ideal clock pins.

I have this doubts

1) If a combination circuit has two inputs,one input is ideal and another one is
non-deal .I think ideal network propagation stops.If so,can i get exact reason.
Correct me if iam wrong
2)The above statement in design compiler. Does this refers to data pin or clock pin.In (PrimeTime/Design compiler), timing arcs considered from clock pin to data output in flipflop.
 

hi,
1. yes, you are right. if A pin is ideal, but B pin is not, so output Y pin is not becoz timing arc from B to Y is not ideal

2. whatever ideal on D pin or CK pin, Q/QN pin is not ideal
 

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