mvrthunder
Newbie level 5
hi friends
i am using cadence virtuso of gpdk90
when i checked the output of nmos connecting vdd to both gate and to the drain i am getting vdd on the source side also when i checked the output .
can any one explain me about this why i am getting vdd instead of vdd-vth?
i am using cadence virtuso of gpdk90
when i checked the output of nmos connecting vdd to both gate and to the drain i am getting vdd on the source side also when i checked the output .
can any one explain me about this why i am getting vdd instead of vdd-vth?