doubt:(how clock frequency is divided here?

[edrin_88]

This is the code for cpld xc9572 which has the system clock 32 khz.but how is it reduced to 25 hz?

entity cntr7seg is
port(
clk : in std_logic;
reset : in std_logic;
disp0 : out std_logic;
s0 : in std_logic;
display : out std_logic_vector(6 downto 0)
);
end cntr7seg;
--------------------------------------------------------------
architecture cntr7seg_arch of cntr7seg is
--------------------------------------------------------------
--local signal declaration
--------------------------------------------------------------
signal count : std_logic_vector(14 downto 0);
signal bcd_out1 : std_logic_vector(3 downto 0);
signal clk_4hz : std_logic;
--------------------------------------------------------------
begin
--------------------------------------------------------------
--This process divides the system clock of 32KHz, to scale it
--down to 25 Hz.?? but how?
--------------------------------------------------------------
process(clk,reset)
begin
if reset='1'then
count <=(others=>'0');
elsif clk='1' and clk'event then
count <= count + '1';
end if;
end process;
--------------------------------------------------------------
clk_4hz <= count(14);

 

[amraldo]

It converts the 32KHZ clock to 4HZ clock.
count(14) is toggled every 16384 clock cycle of the 32 KHz.
it toggles every = 16384/32000 = 0.512 sec
complete cycle = 1.024 sec ==> clock ~ 1 HZ
--
Amr Ali

 

[shitansh]

count(0) -- this is clock divide by 2.
count(1) -- this is clock divide by 4.
count(2) -- this is clock divide by 8.
.
.
.
.
count(14) -- this is clock divide by 2^(1+14)


HTH
--
Shitansh Vaghela