doubt about sync process and async process in vhdl

[kommu4946]

Hi all,

what happens if we use synchronous process and asynchronous process in a design.Does it give meta stable values when implemented on board.

 

[TrickyDicky]

Your question isnt very clear. Do you mean synchronous process to synchronous an asynchronous signal? or just synchronous processes in general? Why not provide an example?

 

[kommu4946]

sorry...what happens if we use synchronous process and asynchronous process in a design...

process(clk,rst)
begin
if(rst='1')then
a<=(others=>'0');
elsif( clk'event and clk='1')then
a<=b;
end if;
end process;

synchronous process

process
begin
wait until ( clk'EVENT and ( clk = '1' )  ) ;
if(rst='1')then
c<=(others=>'0');
else
c<=a;
end if;
end process;

does c gets any metastable value..

 

[FvM]

The asynchronous reset must be released synchronous to clock to avoid timing violations and among other issues metastable states.

Similarly all inputs to the synchronous process must keep setup and hold timing requirements. Using an reset signal with unrelated timing in a synchronous process won't be better than case 1.