steven852
Advanced Member level 4
Hi,
I am looking at this reset implementation and have a big doubt:
always @(posedge clk or negedge reset1 or negedge reset2) begin
if (!reset1) begin
// reset a set of registers to value set 1
end
else if (!reset2) begin
// reset the same set of registers to value set 2
end
else begin
// normal state machine
end
end
The first problem is that I think synthesis only take one "or" in the always list. The second one is that how this implementation could be realized in hardware. There may be race condition between reset1 and reset2 but I am more worrying about the circuit. The third one is whether a better solution is available.
Thanks
I am looking at this reset implementation and have a big doubt:
always @(posedge clk or negedge reset1 or negedge reset2) begin
if (!reset1) begin
// reset a set of registers to value set 1
end
else if (!reset2) begin
// reset the same set of registers to value set 2
end
else begin
// normal state machine
end
end
The first problem is that I think synthesis only take one "or" in the always list. The second one is that how this implementation could be realized in hardware. There may be race condition between reset1 and reset2 but I am more worrying about the circuit. The third one is whether a better solution is available.
Thanks