Doubt about racing at JK-FF

[khaila]

Supposed we have a JK-FF that its J'input tied to START signal and its K'input and its RESET tied to STOP.
START and STOP are synchronized to CLK.

When rising CLOCK and START goes HIGH then the FF'output goes HIGH.

What will happen if later START goes HIGH???
is there any problem with this implementation????

 

[deepu_s_s]

Re: Racing at JK-FF

did u mean that starts goes high after some delay when clock goes high? the output will be effected after some delay......


the change in input signals are visible only as long as the clock is in high state, as ff is a level triggered one


plz correct me if i am wrong


thanks and regards
deepak

 

[khaila]

Re: Racing at JK-FF

did u mean that starts goes high after some delay when clock goes high? the output will be effected after some delay......


the change in input signals are visible only as long as the clock is in high state, as ff is a level triggered one


plz correct me if i am wrong


thanks and regards
deepak

I intended that at the rising edge of the clock START goes HIGH (and STOP is LOW), which mean that FF will smpale the inputcorrectly so its output will goes HIGH.