double gate mosfet project

[siddhiqvlsi]

Hi,

Iam doing my final year project on double gate mosfet using finfet 32nm....
I have simulated the full adder using cmos logic styles such as pass transistor logic, conventional logic etc......

My results for power and delay are better for conventional than pass transistor logics which is expected to perform better....am using the 28 transistor model for conventional logic...simulation is done using hspice.....

Also varying the load capacitance varies the power-delay characteristics and at CL=10pf ,cpl(complementary pass transistor logic) is said to be performing better than conventional and it varies for different CL.....Can any one please help me?.....what is the optimum value for CL?....

Also i want to know how to design weak pmos transistor for complementary pass transistor logic...pls help me....
Thanks in advance...

 

[erikl]

... CL=10pf

10pF is a tremendously large load capacitance value for a logic cell, and this for a 32nm process. Didn't you think of 10fF ?

.....what is the optimum value for CL?....

The actual load of driven cells, i.e. Cin*fanOut. Should be of the order 100fF .. 1pF

how to design weak pmos transistor for complementary pass transistor logic

In terms of logic cells, a weak transistor is a transistor with W/L < standard_W/L of the same type. Say a factor of 3 .. 10 less.

 

[siddhiqvlsi]

10pF is a tremendously large load capacitance value for a logic cell, and this for a 32nm process. Didn't you think of 10fF ?


The actual load of driven cells, i.e. Cin*fanOut. Should be of the order 100fF .. 1pF


In terms of logic cells, a weak transistor is a transistor with W/L < standard_W/L of the same type. Say a factor of 3 .. 10 less.

Thanks for ur reply...