DOUBLE EDGE TRIGGERED FLIP FLOP design... transistor size??

[shyayada]

HI
I am designing a double edge triggered flip flop for LOW POWER CONSUMPTION.
Can anyone help me in deciding the transistor size of the NMOS AND PMOS used in it.
I have been suggested to use .25 micron

my voltage limits will be from .8 to 3 volts.

 

[satishtiwari01]

Re: DOUBLE EDGE TRIGGERED FLIP FLOP design... transistor siz

you can use logical effort to determine the size of transistors on the critical path.
you can check this link

https://en.wikipedia.org/wiki/Logical_effort