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DOUBLE EDGE TRIGGERED FLIP FLOP design... transistor size??

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shyayada

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HI
I am designing a double edge triggered flip flop for LOW POWER CONSUMPTION.
Can anyone help me in deciding the transistor size of the NMOS AND PMOS used in it.
I have been suggested to use .25 micron

my voltage limits will be from .8 to 3 volts.
 

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