# Dont understand the meaning of this LOOP (VHDL)

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#### BlackOps

##### Full Member level 5
I am studying the VHDL code generated by the Peripheral Wizard in EDK 9.1

there is such piece of code:
Code:
        for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8 to
(byte_index-(byte_index/(C_DWIDTH/8))*(C_DWIDTH/8))*8+7);
end if;
end loop;

C_DWIDTH = 64

for example, if byte_index is 4.. then: (4 - ( ( 4/8 ) * 8 ) ) * 8 = 0, dosnt matter what is value of byte_index, Bus2IP_Data will always have value of [0 to 7] inside...

then why does the wizard not just writes Bus2IP_Data(0 to 7) ?? why is it using such complicated equation? or i am wrong somewhere?

thanks

#### teddyzhai

##### Newbie level 1
I think, this "user logic" file is just a generic template generated by EDK. It is parametrized.

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