Does Xilinx's Spartan-IIE support gated clock design?

[no_mad]

gated clock xilinx

Hi all,

Can ISE handle clock muxing design?

Please enlighten me.

Thanx in advance,
-no_mad

 

[calong]

u should goto www.xilinx.com and search for "gated clock",gated clock was always used in low consumed power ASIC design, the "gated clock" write by yourself has some problem in FPGA and slow down your clock speed.

 

[it_boy]

Hi no_mad,
SpartanII2 does not support standard clock multiplexers (BUFGMUX) that is available in the later devices, but you can still use gated clocks in your designs (synthesis tool does not error out), but tool will warn you as the skew while using gated clocks is difficult to determine.
Depends mainly on your design and frequency of operation and how you floorplan if necessity arises.