Dear all,
I have a design (Adder block + VerilogA block). When I try to simulate my design with spectre it produces a netlist file called "netlist" and 2 other files called "netlistHeader" and "netlistFooter". What I was wondering about is does the "netlist" include my full design (that is Adder block + VerilogA block) or it only includes my Adder block. and I have to do a "cat command" to get my final netlist.
when i have checked my "netlistFooter" file it has ahdl_include to my VerilogA file.
Thanks and Regards,
Kamesh.