Does oversampling ADC require S/H circuit?

[ee484]

Hi, does delta-sigma ADC requires S/H circuit? (Discrete-time)

Any good reference?

 

[FvM]

No, as the DS circuit is already sampling the input signal.

 

[safwatonline]

yes, it needs AAF and S&H

 

[FvM]

It may depend on the circuit, if an explicite S/H or T/H stage is required. In an abstracted signal processing analysis, input signal sampling is implied with discrete time DS modulators anyway. Thus I agree.

 

[ee484]

I agree that it requires AAF, but S/H as well??
Can Anyone recommend paper/dissertation that uses S/H for DS modulator?

 

[FvM]

I don't remember a circuit with explicite S/H, but time-sampling is often shown as first stage in a discrete-time DS ADC block diagrams.

This is the case e. g. in Rabii/Woley The design of low-voltage, low power sigma-delta modulators. The circuit actually used in their experimental implementation has a differential SC integrator as first stage with two inputs, one for the signal and one for the feedback. That's an example of the DS circuit is already sampling the input signal, as I mentioned. From a circuit design viewpoint, I would say, the S/H stage is omitted, but you may say, the SC integrator is a S/H, if you like.

 

[caosl]

Switch capacitor circuit sample the signal already. I think it needn't the S/H stage.