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Thanks crutschow, Just thinking that reduced common mode will reduce gm, that increases the mismatch contribution from the load devices. Considering the relation: (gm_diff/gm_load)*Vth_mismatch_loads
When common mode position drives the front end into a
linear region (MOS) or saturation or near-cutoff (BJT)
the gain will be reduced. The common mode position at
which this rolls on, is process / temp / voltage variable.
So at extreme common mode positions you may see
"enhanced" process sensitivity (like, if you're 0.5V from
the lower rail with a NMOS front end, and VTN varies
0.3 - 0.7V, half of the distribution might be into cutoff
of the diff pair tail current and gain tanks, bandwidth
pulls in, etc.).
This is why rail-rail input stages are interesting.
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