Does metal (copper, aluminum) shielding really help inductors in ICs?

[vlsi_design2]

In ICs, the inductors can magnetically couple to the the substrate and cause eddy current to flow which causes power loss (emf^2/Rsub). To minimize this people put metal (copper, aluminum) shielding below the inductor to prevent magnetic lines of from from reaching substrate. Now the catch is both copper and aluminum have mu_r =1 i.e. they will pass all magnetic lines of force to the substrate. How can they help in shielding magnetic coupling? If iron were used then it might make sense but ICs do not use iron usually. Therefore, what is the mechanism?

 

[FvM]

Metal shields block AC magnetic fields by creating eddy currents. Depending on frequency, conductivity and thickness, the field is more absorbed by loss creation or mostly prevented from penetrating the metal.

 

[dick_freebird]

You don't want a shorted coil under, over or near your
inductor. RF people use lightly doped trap rich substrates
(high R) underneath a buried oxide (infinite R) to tamp
down eddy losses which de-Q an inductor.

"People do" stupid things for stupid reasons, on occasion.

Small signal inductors at RF are not going to spray a lot
of magnetic field. It can be enough to matter, to on-chip
circuitry (just like any other interconnect-radiator; don't
forget about longitudinal AC currents in straight wires
either, seen those hose a GPS LNA with clock signal harmonics,
thanks to a customer's lame ("low cost") frequency plan....

I believe you're best off with some "substrate engineering"
(or simple selection) like I describe. Or, you declare the
presence of RF magnetic fields and make it the customer's
module / PCB construction problem.

 

[volker@muehlhaus]

people put metal shielding below the inductor to prevent magnetic lines of from from reaching substrate.

Pattern ground shield in RFIC inductors has a different purpose: it captures the electric field that would otherwise couple to the lossy silicon substrate.

I have been active in RFIC inductor modelling on Si/SiGe for almost 20 years now. The topic of "eddy currents in the substrate" was a common misunderstandig in the early days, until it was shown by substrate current visualization that most substrate current flow perpendicular to the inductor loops - just capacitive coupling from the coil metal to silicon below, and that current flows to some remote ground, or couples back to other parts of the coil. That capactive coupling to the substrate is the main substrate loss mechanism, which we also find in equivalent circuit modelling.

To have a practical issue with eddy currents (H field couling), the substrate conductivity would need to be much higher.

Patterned ground shield is a trade-in: you get rid of the lossy R||C in the shunt path, but have increased capacitance to the shield.

 

[BigBoss]

Polysilicon zig-zag pattern is generally used to decrease Eddy effect in RFIC circuits.