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Does Latency is more important or Skew is more important?

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vlsitechnology

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Can anyone tell me does latency has more importance or skew?

Which one effects our design? Skew or Latency?
 

pmat

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Re: Does Latency is more important or Skew is more important

They both affect the design. Concerning, which affects more, it depends... However, most are worried about the skew, as it directly affects max freq, hold violations etc.

Pavlos
 

vlsitechnology

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if latency is more then how it effects our design? I guess overall we c skew bcz skew itself is difference between the two latencies am i right?
We don't bother how much is the latency we need minimum skew

How more is ur latency and how less is ur latency is determined by the skew that is difference between the two latencies..

correct me if i am wrong..........
 

yibai

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Re: Does Latency is more important or Skew is more important

in fact, we hope latency and skew are both smaller.
if we need run higher frenquency, the skew is more important.
but, lantency more, we cannot balance the skew, the skew maybe more.
 

Nandy

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One signal drives 10 destination. There are 10 delays from the source to the destinations. The difference between them is skew. You can call the the average delay as the latency.
 

papertiger

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latency may cause removal/recover time violation unless you put constraints on the reset path too.

another issue may be OCV.
 

JeffBuckles

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Re: Does Latency is more important or Skew is more important

As others have said, it does depend greatly on your individual application. But a good rule of thumb to help you decide which is more important to your design is that synchronous interface timing depends more strongly on latency ("clock insertion delay") while internal register->register timing depends more strongly on clock skew (difference between clock arrival times at the registers).

Skew is not necessarily bad. And minimal internal clock skew should not normally be a goal in itself -- it is a just one part of an overall strategy to meet internal timing path requirements. Skew can sometimes even be used intentionally to improve timing paths ("useful skew").

And like papertiger mentioned, as insertion delay (latency) increases, OCV effects increase. Careful design of the clock tree can mitigate some small portion of this effect in many cases.

You will usually have to decide which is more important to your specific design because they are conflicting goals. Reducing skew will usually increase latency because you will be adding more delay to make the shortest paths as long as the longest paths, and individual branches in the clock tree will, on average, have smaller fanout with more levels in clock tree. Conversely, optimizing for minimum latency will probably result in greater skew because of fewer clock tree levels, higher fanout at each level, and less skew-balancing delay added to the fastest paths.

Best Regards
-- J.
 

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