Re: Does dividing the a CLOCK by sequential logic is permitt
Yes, you can use clk/2 clock. But iInternally generated clocks are giving rise to testability issues, because the logic driven by an internally generated clock can't be
made part of the scan chain. Writing timing constraints for generated
clocks becomes more difficult as well.
Solution: Add in test circuitry to bypass the internally generated clock.
For example, if you have a divide-by-2 clock, add in a MUX to
select a primary input clock over the internally generated one
for test. The MUX select line should be controlled by a
test-mode signal coming from a primary input.