Does dividing the a CLOCK by sequential logic is permitted??

[khaila]

generated clock from mux

Supposed we have CLK.
A block need CLK/2.
In order to generate CLK/2 I used D-ff that its input is drived by its Qn.

Can I use this CLK/2 in my design??? so I will have two clock domains!

Does dividing the a CLOCK by sequential logic is permitted in ASIC design???

 

[rameshsuthapalli]

Hi,

divide logic by a sequencial block is permited.

regards,
ramesh.s

 

[quan228228]

Re: Does dividing the a CLOCK by sequential logic is permitt

We can use combinational logic and sequential logic in clocl divider.

In RTL design, we concern functionality. In layout and CTS(clock tree synthesis), we concern timing of clock network.

quan228228

 

[dft_guy]

Re: Does dividing the a CLOCK by sequential logic is permitt

Definitely, you can use clk/2 in your circuit, but be careful during DFT mode. With your clock divider now sourcing the clocks going to your flops, the ATPG tools won't know how to drive them. So you must bypass this divider in scan mode.

John
DFT Digest

 

[barkha]

Re: Does dividing the a CLOCK by sequential logic is permitt

Yes, you can use clk/2 clock. But iInternally generated clocks are giving rise to testability issues, because the logic driven by an internally generated clock can't be
made part of the scan chain. Writing timing constraints for generated
clocks becomes more difficult as well.

Solution: Add in test circuitry to bypass the internally generated clock.
For example, if you have a divide-by-2 clock, add in a MUX to
select a primary input clock over the internally generated one
for test. The MUX select line should be controlled by a
test-mode signal coming from a primary input.

 

[shiv_emf]

what is need of clk/2??

 

[xinsu]

you can set up two mode to do timing analaysis in STA