Does digital design has "post simulation"(after ex

[irun2]

Hi all,
I've designed a controller using verilog, after compilation and P&R, I exported the GDSII file for Cadence to import to run the DRC and LVS, and after all that passed. I extracted the layout and wanted to do the post simulation like all analog designers do. In order to function the stimulas, i've created two blocks too to generate the signal I want(import the gate netlistes to Cadence)

I've created a schematic including that two blocks, opened ADE and setup all needed. But when I started to run the sim, about 11 errores detected, all of them are the like, "Cell view analog_extracted INLHDX1 of library DCELL..was modified since last extraction.." if I recall correctly. But i've never modified that mentioned. I replaced that 2 blocks with analogLib signals and did the sim again, it worked!

Seems to me the 2 blocks need to be extracted in their layout view?

Even I can run the post simulation after extraction, but it's very slow since it uses SPICE! So does digital design has "post simulation" after all? If so, what tools do we need?

Or post gate-level simulation is enough to ASIC?

 

[jbeniston]

Usual flow for digital ASIC is:

- post-layout simulation in min/max corners (ModelSim / VCS / NCSim)
- STA (PrimeTime)
- RTL to post-layout logical equivalence check (Conformal / Formality)

 

[rca]

as mention by jbeniston, you can add some gated simulation with timing annotation (from STA tools), to confirm the behavior is the same.

in our company, we only done the gated simulation with timing to check the scan patterns, for the functionnal mode, LEC & STA are the minimum require.

best regards.