Does anybody know how to calculate read and write delay for 6T sram using hspice.

[oly]

Does anybody know how to calculate read and write delay for 6T sram using hspice. here is my hspice code for read and write.

*sramcircuit..
.lib "45nm_model.txt" cmos_models
*.temp=80
*.global vd vdd
*.param vd=1.2
vdd 1 0 dc 1.2
vwl 6 0 pwl(0n 0 50n 0 51n 1.2 110n 1.2 111n 0 140n 0 141n 1.2 190n 1.2 191n 0 210n 0)
vwl1 7 0 0 
vwl2 8 0 pwl(0n 0 20n 0 21n 1.2 120n 1.2 121n 0 210n 0)
vctrl 10 0 pwl(0n 0 20n 0 21n 1.2 120n 1.2 121n 0 210n 0)

m1 2 3 0 0 nmos w=45n l=45n
m2 3 2 0 0 nmos w=45n l=45n
m3 2 3 1 1 pmos w=135n l=45n
m4 3 2 1 1 pmos w=135n l=45n
m5 4 6 2 0 nmos w=90n l=45n
m6 5 6 3 0 nmos w=90n l=45n
m7 4 7 1 1 pmos w=45n l=45n
m8 5 8 1 1 pmos w=45n l=45n
m9 5 10 0 0 nmos w=90n l=45n

.OP
.option nomod
.protect
*.print tran v(2) v(3)
.tran 1n 210n
.option post 
.end

please help.Thanks

 

[andre_luis]

Why don´t you simply measure that graphically by cursors at simulator output on transient window ?

 

[KlausST]

Hi,

I´m not sure ... are you talking about DRAM or SDRAM timing?

i´m not up to date with DRAM timing. But unlike static RAM where you can determine the acess time very precisely, you can not do this with dynamic ram.
It´s because they use a protocol with instructions and data. So the total (average) access time depends on memory addressing, block size and access mode and the timing for refresh.

This is what i know from devices years ago, maybe newer devices work in a different way.

Klaus

 

[FvM]

I´m not sure ... are you talking about DRAM or SDRAM timing?

The netlist seems to describe static RAM, so does the title.

 

[KlausST]

Hi,

yes, now i see.. some days are crazy....

sorry.
Klaus

 

[oly]

is there any formula in hspice tool to simply measure read delay and write delay for 6T sram?

 

[oly]

Thanks for d replies but i m not getting anything.so please elaborate how can i do dat.

- - - Updated - - -

Why don´t you simply measure that graphically by cursors at simulator output on transient window ?

It gives me values but it can only give values for one waveform if we want to locate values at different times then it would be hectic.so what can i do?

 

[oly]

[Moved]SNM Simulation - Hspice - Butterfly curve

trying to simulate snm with this code but as i know that butterfly curve is found by the output of two inverters but i cant found the curve with that two points.i am working in 45nm technology.can you explain me how i can do it.
Thanks in advance

 

[cajjdnej]

Re: [Moved]SNM Simulation - Hspice - Butterfly curve

For a 3T Dram
Maximum voltage after write 1 is always Vprecharge-Vthreshold
and after read 1 it is always (Vbitline-Vprecharge)(Cbit/Cpre+Cbit)
Follow the same for 6T Sram too...It is a verified result