Does any simulator plot the hysteresis of a comparator?

[sumitj]

comparator design

Hi all

I wanted to know does any simulator plots the hysteresis characteristics of comparator. I am doing a 2 stage cross coupled comparator design as discussed in allen holberg. (with two feeedback loops).

There are some oscillations when the comparator makes transition from high to low. Can this be because of very less rise and fall time of input pulse ?

What input should be applied to check for comparator hysteresis?

Thanks

 

[sunking]

comparator design

run .dc and .tr

 

[Karthikeya]

Re: comparator design

hi
can u upload the transient simulation results and schematic?this will help us understand better.
are the oscillations only during the h-l transition? this problem can occur if pmos is made strong enuf that input cant override the data at the output....

regards

 

[surajit]

Re: comparator design

By two DC analysis, Vi+ is going from -ve to +ve over Vi- and vice versa, you can measure.

 

[hojjat-kaveh]

Re: comparator design

can u upload the transient simulation results and schematic?this will help us understand better.
are the oscillations only during the h-l transition? this problem can occur if pmos is made strong enuf that input cant override the data at the output....

 

[yorande]

comparator design

i try that circuit in the book too.
I use a large sinewave to do it.
The transient output rise and fall at different input voltage, I think this shows the hysteresis performance.
But I don't see oscillation.

 

[abcyin]

comparator design

increasing the rise and fall time is also OK