svensl
Full Member level 1
This has puzzled me a bit today.
Scenario 1)
Consider a fractional-N PLL. The VCO frequency goes into a chain of 2/3 dividers which are set by the sigma-delta modulator. The SDM works with a 16bit input word and produces a 3 bit output. Hence the divider divides by either N-3, N-2, N-1, N, N+1, N+2, N+3, N+4. The output will be approx. 26MHz.
Scenario 2) same as above, but the VCO frequency is divided by a fixed factor of two before going into the divider. The SDM has the same resolution, so the fractional part should be represented with the same accuracy. Only the N number is smaller now as we need to divide only by half as much.
Q) Will there be a difference in accuracy of the clock produced at the output of the divider?
From a mathematical point of view there should not be any difference as the SDM which produces the fractional part has the same accuracy.
However, intuitively, I could also argue that since the periods of the input to the FB divider are larger in scenario two, the FB divider will have less "resolution" in dividing it down (or matching to) to 26MHz.
Could anyone please share their thoughts on this topic.
Regards,
Ps. The divider used is from:
A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology
Scenario 1)
Consider a fractional-N PLL. The VCO frequency goes into a chain of 2/3 dividers which are set by the sigma-delta modulator. The SDM works with a 16bit input word and produces a 3 bit output. Hence the divider divides by either N-3, N-2, N-1, N, N+1, N+2, N+3, N+4. The output will be approx. 26MHz.
Scenario 2) same as above, but the VCO frequency is divided by a fixed factor of two before going into the divider. The SDM has the same resolution, so the fractional part should be represented with the same accuracy. Only the N number is smaller now as we need to divide only by half as much.
Q) Will there be a difference in accuracy of the clock produced at the output of the divider?
From a mathematical point of view there should not be any difference as the SDM which produces the fractional part has the same accuracy.
However, intuitively, I could also argue that since the periods of the input to the FB divider are larger in scenario two, the FB divider will have less "resolution" in dividing it down (or matching to) to 26MHz.
Could anyone please share their thoughts on this topic.
Regards,
Ps. The divider used is from:
A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology