Hi,
I am new to SystemC based verification/design. I am familiar with Vera/verilog/vhdl. I would like to learn SystemC in a systematic way. Is there any systemC methodology document like Vera rvm,Specman eRM? Please suggest some way to create a simple code and compile/simulate the code.
It is strange to here that, because I examined these links before posting the message. There is another way to find these books on the forum : use search with keyword "SystemC" and search option forum = EDA E-books Upload/Download
systemverilog would be good & powerful. At the same time it is very costly.
systemC is an open standard and we can use C++ compiler to achieve many things.