Re: PLL input clock
To ensure stability, good spur attenuation and linear behavior, the loop bandwidth of the PLL should be = fref/10 .So, if you ensure that and for very low reference frequency, your loop bandwidth would be extremely small, leading to a very large settling time .So, you should ensure first thst your PLL is stable, then you should try to increase the reference frequency for faster settling .You can increase the reference frequency without being constrained with the frequency step by using fractional-N architecture .