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Yes, you almost always need some capacitance at the output. Older NPN based regulators (like the 78xx) series are pretty stable and they don't need much output capacitance. This is because they are based on an emitter follower which has very low output impedance.
PNP or PMOS based low-dropout regulators (also known as LDOs) do require much larger capacitance for stability. Further complicating the issue is that the capacitor must have some equivalent series resistance (ESR). The ESR (which is an inherent part of the capacitor) together with the capacitance itself gives rise to a transmission zero in the loop gain transfer function and this helps to stabilize the system. It turns out that the ESR value must not bee too high or too low otherwise the phase margin of the system will be too low for a proper design. Most manufacturers will specify the range of ESR that is needed for their regulators.
So if you use a real *good* capacitor with very low ESR at the output of your LDO, you will surely get lots of oscillations at the output of your regulator. So in this case better component does not translate into a better or more reliable design.
Take a look at this PMOS-based LDO **broken link removed**
The plots on page 9 show the region of stability for given ESR values.
Yes, NMOS should in theory not require a capacitor, but I think you still need something out there because you don't want your phase margin to be anything less than 45 degrees. So if you have a good loop gain with a large gain at low frequencies and crossing the 0dB point with -20db/decade slope, the system should be pretty stable. The power supply rejection ratio tells us how sensitive the system stablity is to changes in the input voltage. If you have a large enough low-frequency loop gain the PSRR shoud be inversely proportional to the loop gain.
Yes, NMOS should in theory not require a capacitor, but I think you still need something out there because you don't want your phase margin to be anything less than 45 degrees. So if you have a good loop gain with a large gain at low frequencies and crossing the 0dB point with -20db/decade slope, the system should be pretty stable. The power supply rejection ratio tells us how sensitive the system stablity is to changes in the input voltage. If you have a large enough low-frequency loop gain the PSRR shoud be inversely proportional to the loop gain.
Well, I believe the PSRR is a transfer function itself so it does have frequency response.and it will be effected by the poles of the system. This transfer function is from a disturbance on the input voltage to the output so it is better to have lots of attenuation at the frequencies you are interested in having rejection.
I have read a few journals, mentioning that putting a Caps (no matter internal or external) will help in high freq noise rejection in a LDO design for both NMOS and PMOS pass transistor. In the forum by surianova, you mentioned that for NMOS pass transistor , it is not necessary to have caps as the output impedance is low and this if you add any caps will only alter the high freq poles in minor. So, in this case how do i convince myself for a NMOS pass LDO design? Is that necessary to have this caps for high freq noise rejection????
I think you should put some caps at the output. What I meant to say is that you can make it work without the capacitor if you know that your load, input and temperature range is limited. But this would be a marginal design. For any kind of a real product, we always recommend caps at the output (and the input). Sorry, I should have said things more clearly. Sometimes I am thinking it but in the haste of writing the message the information does not get typed in.
I have observed that if the UGB of the ampr. is less then the PSRR starts to degrade at high frequencies.Even it goes to positive values at hogh freq.Any explanation for this?
Regards,
Jitendra.
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