hi everyone...
Do the cell libraries that we use during synthesis contain standard cells for comparators....? i.e when we use comparison operators like <>= in the HDL , will they be replaced by compartor standard cells during synthesis...?
Is it better to design comparator using logic gates or to use the <>= symbols to realise the operations, considering the delay of the module...
Syhthesis will use designware components to replace hdl code.
if standard cell dont have this comparator, DC tool will transfer corresponding standardcell to replace designware components in optimal situation
Usually in std cell libraries u dont find comparators, multipliers, carrylookadder etc,
if u r using design complier, then synopsys will provide these components with the dc tool, interms of designware components.