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DNL of flash converter

yefj

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Hello, i have a flash ADC converter with 1V vref and idial ressistors but in the comparator i have standart deviation of 3mV.
how do i calculate from the the standart deviation of the whole device(DNL INL)?
I have found a similar manual for the ressistor mismatch in flash ADC as shown bellow.
But in general i am having problem connecting comparator mismatch with total output mismatch (DNL INL)
Thanks.

1.JPG
 

sutapanaki

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What portion of the LSB is 3mV?
You can think of the comparator offset as referred to the reference resistor ladder since you are more familiar with variations in the resistors. If you imagine the resistor ladder is ideal but you have input referred offset voltage of the comparators placed in the comparator input that connects to the ladder, then equivalently you can think of comparators as ideal but resistor taps moving with the offset. The resistor ladder is like a thermometer DAC, so with the variation that you already know, you can calculate the sigma of the DNL and INL of that DAC and most probably it will reflect almost directly as DNL and INL of the ADC.
You can also try to estimate the worst DNL. Imagine 3 consecutive ADC thresholds for two consecutive code widths. If the 1st threshold moves to the left by 3 sigma, the 2nd threshold moves to the right by 3 sigma and the 3rd threshold moves to the left by 3 sigma, then you will have the first code width (between thresholds 1 and 2) that is wider by 6 sigma and the second code width that is narrower by 6 sigma.
Apart from that you can create, say a matlab model and vary randomly the comparator threshold and plot DNL/INL.
 

yefj

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is there some manual which you could reccomend me for this problem?
Thanks.
 

sutapanaki

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Probably there is. I can't imagine there isn't. I can't think of any off the top of my head. Just search the net or Analog devices' website.
 

yefj

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What portion of the LSB is 3mV?
You can think of the comparator offset as referred to the reference resistor ladder since you are more familiar with variations in the resistors. If you imagine the resistor ladder is ideal but you have input referred offset voltage of the comparators placed in the comparator input that connects to the ladder, then equivalently you can think of comparators as ideal but resistor taps moving with the offset. The resistor ladder is like a thermometer DAC, so with the variation that you already know, you can calculate the sigma of the DNL and INL of that DAC and most probably it will reflect almost directly as DNL and INL of the ADC.
You can also try to estimate the worst DNL. Imagine 3 consecutive ADC thresholds for two consecutive code widths. If the 1st threshold moves to the left by 3 sigma, the 2nd threshold moves to the right by 3 sigma and the 3rd threshold moves to the left by 3 sigma, then you will have the first code width (between thresholds 1 and 2) that is wider by 6 sigma and the second code width that is narrower by 6 sigma.
Apart from that you can create, say a matlab model and vary randomly the comparator threshold and plot DNL/INL.
Yes thats the problem i know that i have certain voltage offset in each comperator but if we look at the slide bellow,i cant link my offset of the comperator to these formulas.
to calculate the total DNL INL
1.JPG
 

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