Hi FvM,
Preface: lengthy answer is not confrontational, intended to add to what I think you meant. It's well-considered because I just want to check simulation to reality differences for now.
Accuracy of log/antilog analog computing circuits is mainly limited by non ideal transistor characteristics, type variations and intra pair junction temperature differences.
Thanks, hadn't even considered such a point. Not expecting miracles here, just having a look to see if it's worth proceeding further (unlikely) to make an SMD proto board. Using matched dual soics (shame have no matched quad package here) and at present a TH quad OA.
Increasing Vce above the necessary saturation margin will immediately increase thermal mismatching effects by larger transistor power dissipation, thus I wonder if the revised circuit is well considered.
Increasing Vce above the necessary saturation margin... - it would take me a while or more of studying BJT basics (again) to even genuinely pretend to understand that in practical terms and apply it diligently.
thus I wonder if the revised circuit is well considered.
This is "Mr. hobbyist" we're talking about, so I think we both can assume
not well considered nor well understood are givens.
In case you're interested, which I doubt much - from simulation to breadboard "rough sketch" of only the multiplier divider circuit:
V+ = 4.82V (should be +4V)
Using SOT-23 ref (LM4041) with 10k TH trimmer to get 1V for E1 and E2
TO-92 ref (TL431) a) downstream of TH TC7660 to buffer it (get -3.98V) and b) another in place of Zener (another meaning TL431)
two SOIC dual matched BJTS (NSS40301) and a TH quad OA (LMC6464)
replaced 1k resistors with 10k resistors (all measure between 9.91k and 9.93k) and 10R trim with 1k trimmer (measures a miserable 937R total)
Used 100k trimpot to get input from 0.99V to 1.01V (small range is the area of interest to measure/check a 1% 1GOhm resistor someday hopefully for another circuit where that +-1% would ruin low value capacitor measurements)
A few nasty-looking but unavoidable 5cm antenna wires here and there...
= Output/Result is surprisingly faithful to simulation but a couple of mV off in one direction.
Some of the nodal voltages are quite different to the simulator's nodal voltages.
Simulation is precise with 1V in +-100mV. Breadboard starts to be 30mV to far worse not far away from the 1V +-10mV range.
Conclusion: better than expected (thought it would be grossly different to simulation) (very unlike a discrete current/voltage source that was brilliant in simulations and verging on the criminal in reality and a waste of time and components); about as inaccurate as expected as well; needs a lot more exploring to see where discrepancies are coming from. Won't be going into mass production yet.
Not sure what you meant by "true potentiometer circuit" - Besides sounding suspiciously like "This will be right with just one, or two or three or more components/sub-blocks", do you mean a logarithmic potentiometer?