Division in xilinx ultrascale+ using DSP

[beginner_EDA]

Hi,
I have a design running at 125 MHz (8ns Pulse) and I do a large number division (125000000/115200) in system Verilog and it consumes 43 LUTs and 130 CARRY8 and have 34.087ns data path delay and that leading to -26.233ns setup timing violation. I would like to do it using dsp/ip core, if it helps to pass timing.
I saw a documentation here:

https://www.xilinx.com/support/documentation/user_guides/ug579-ultrascale-dsp.pdf

but I am not sure if it is the write one for this purpose.

 

[std_match]

Are both the dividend and the divisor constants? If so, why doing the division in logic and not at compile time?
If using logic, do you need to do the division in one clock cycle? If not, do it in a simple state machine (long division).

 

[beginner_EDA]

Are both the dividend and the divisor constants?

dividend and the divisor vary. I think this is the write one: https://www.xilinx.com/support/documentation/ip_documentation/div_gen/v5_1/pg151-div-gen.pdf

 

[dpaul]

Maybe some udeful info here-

http://forums.xilinx.com/t5/Xilinx-...-power-of-2-integer-division/m-p/1121756#M979

 

[TrickyDicky]

This is your original post, there are some answers there: http://forums.xilinx.com/t5/Synthesis/Division-in-ultrascale-devices/m-p/1156181#M36401
Why do you need to complete the division in a single clock - why cant it be pipelined?

 

[beginner_EDA]

Why do you need to complete the division in a single clock - why cant it be pipelined?

I don't need it in a single clock and can be pipelined. However the requirement is not to use Xilinx IP(divider) but just DSP blocks. Can you point me to such design from Xilinx if you already know?

 

[std_match]

I don't need it in a single clock and can be pipelined. However the requirement is not to use Xilinx IP(divider) but just DSP blocks. Can you point me to such design from Xilinx if you already know?

You probably don't gain anything by using one or more DSP blocks for this. Do a simple state machine in "pure" VHDL/verilog instead.

 

[TrickyDicky]

Is there any reason for not using a Xilinx divider IP? Also any reason you cannot use a LUT?

 

[beginner_EDA]

Is there any reason for not using a Xilinx divider IP? Also any reason you cannot use a LUT?

IP -> complexity reason. LUT can be used. How to use LUTs for the division in pipelined format that passed timing?

--- Updated Sep 30, 2020 ---

You probably don't gain anything by using one or more DSP blocks for this. Do a simple state machine in "pure" VHDL/verilog instead.

can you give me some hints how to write Verilog for division. I saw some radix 2 algorithm but its seems to be not easy.

 

[ads-ee]

Non-restoring division algorithm is much simpler than a radix-2 division. All it uses is addition and subtraction. You probably don't even need to write it yourself, you can probably find code for it if you do a search.

Here is an easy to follow description.
https://www.geeksforgeeks.org/non-restoring-division-unsigned-integer/

It's not something you can pipeline so you have to clock it as many times as there are bits in one of the operands (don't recall which and too lazy to look it up ) to get one result.

 

[beginner_EDA]

@ads-ee Hi, is it allowed to post on this forum the instantiation code of only DSP block I see under ultrascale+ device "DSP48E2" ? I have some question about setting some parameters of it.

Furthermore If I do addition (A<=A+M) or subtraction(A<=A-M), how I know if synthesis tool/vivado utilize LUTs or DSP block (e.g. DSP48E2) for this? DO I have to set additionally something in synthesis tool/vivado to say use DSP block and not LUTs?
or I must have to instantiate DSP48E2 and configured accordingly, if I want to use DSP block in ultrasclae+ devices for this purpose.

I am asking because I am not sure even 32 bit addition and subtraction for the algorithm you mentioned can lead to timing violation which I have.

 

[dpaul]

The Ops post #6 -

However the requirement is not to use Xilinx IP(divider) but just DSP blocks.

Did you read this document which tell how to use the DSP48E1 Slice for division?
https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

 

[std_match]

Furthermore If I do addition (A<=A+M) or subtraction(A<=A-M), how I know if synthesis tool/vivado utilize LUTs or DSP block (e.g. DSP48E2) for this? DO I have to set additionally something in synthesis tool/vivado to say use DSP block and not LUTs?
or I must have to instantiate DSP48E2 and configured accordingly, if I want to use DSP block in ultrasclae+ devices for this purpose.

I am asking because I am not sure even 32 bit addition and subtraction for the algorithm you mentioned can lead to timing violation which I have.

If you want to use the DSP block for addition/subtraction, either instantiate it or look in the documentation if there is a way to infer it.
If 32-bit LUT operations give you timing violations, you can create a strobe every second/third clock cycle for the operations, and set the corresponding timing constraints as "multi-cycle". You have a lot of options for fixing timing violations when the throughput isn't important.

 

[ads-ee]

@ads-ee Hi, is it allowed to post on this forum the instantiation code of only DSP block I see under ultrascale+ device "DSP48E2" ? I have some question about setting some parameters of it.

I don't see why it would be a problem. Go ahead and post it if you want help with the settings.