[SOLVED] division in FPGA using verilog

[dipin]

Hi,
I am trying to do a code for do division using verilog that is work with fpga. The thing is division operator is not syntyhesizable.I am using fixed point arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there any other possibility
????please help me.

If i get (1/denominator) , then we can scale and can multiplay with numarator and can get the result .Is there any way to get it in FPGA..I dont want to use seperate module for that
regards

 

[axcdd]

division by multiplying by (1/denominator) + scale is as i far know the best way to deal with div. also You can give a try to your vendors division ipcores.

 

[TrickyDicky]

For Xilinx, you MUST use the IP core for a divide.

 

[ads-ee]

Why must? I've implemented non-restoring divide circuits in Xilinx.

Regards

 

[TrickyDicky]

well, you can do what you want as long as you dont use the / function.

 

[ads-ee]

Actually I'm pretty sure Xilinx's tools will accept / function as long as the denominator is a power of 2 (2^N). I usually just write that as a >>N shift, but on occasion I've used / as it made the code easier to read.

 

[shaiko]

Both Alters and Xilinx support the / function for constants and 2^n numbers.
If your application is (VERY) low speed you can also implement a purely combinatorial divider with a custom function.

 

[mrflibble]

Both Alters and Xilinx support the / function for constants and 2^n numbers.
If your application is (VERY) low speed you can also implement a purely combinatorial divider with a custom function.

You know, I've never even tried a constant != 2^n to see what happened. I just use an explicit core generated module and off we go. So out of interest: what does for example xilinx xst synthesize for a division by a constant that is NOT a power of two?

 

[ads-ee]

I tried a simulation testcase of /13 using Vivado and it simulates correctly, but I haven't tried synthesizing it.

- - - Updated - - -

update: Vivado synthesis correctly implemented my divide by 13 testcase. The netlist simulation works exactly the same as the RTL.

 

[dipin]

thanks axcdd,
but how can i get (1/denominator) in fpga.....


the thing is division operator circuit is too big and complex . so i dont want to use that and i dont want to use any ip core too.can any one give me some logic......

 

[axcdd]

it depands if divisor is constant or signal.

 

[arishsu]

Hi
You can use methods like restoring or non-restoring division. But it may not work for fractions. For fractional division you can use floating point methods.

 

[ads-ee]

the thing is division operator circuit is too big and complex . so i dont want to use that and i dont want to use any ip core too.can any one give me some logic......

For fractional division you can use floating point methods.

Floating point in an FPGA? Talk about a huge complex circuit. Now let's not use a core and write one yourself? If the OP needs to use floating point and they don't want a big circuit they should do whatever it is they are trying to do in a processor instead of an FPGA.

You can use methods like restoring or non-restoring division.

I already recommened using non-restoring division in #4.
If they can get away with using fixed point math then they should look into the non-restoring or restoring division algorithm as it's probably the most area efficient way to do division (trading off latency for area) If they use any of the radix-2/4 etc methods they will end up with the big complex circuit again.

Regards

 

[arishsu]

Floating point in an FPGA? Talk about a huge complex circuit.

I agree with that. But I think floating point is the better way to do fractional division(I am not sure). Can we implement a fractional divider using fixed point?

 

[dipin]

please correct me if iam wrong. i think floating point won't synthesize in fpga ,only fixed point will synthesize.In division getting quotient and remainder part is done. But i dont know how to represent remainder as fraction . I am confused with that. normally remainder is represented by 2^-1 for .5
SO IF THE REMAINDER IS 3, in binary it is 0011. but in fraction it is 1100
(.625) approximately

if i do 13/5 gives quotient 2 and remainder 3 but result is 2.6
. but how can i represent it.
so what should i do... pls help me

 

[FvM]

Before deciding about algorithms and implementation, you should figure out useful number formats to handle the problem. Any discrete number format (integer, fractional fixed point, floating point) can be synthesized in FPGA.

I use to try numerical problems by pencil and paper method, sometimes with the help of a pocket calculator. If the algorithm is clear, the implementation will be usually the simpler part.

If you want to get x/y as a fractional number, you'll do an integer calculation 2^n*x/y, in other words append n zeros to the right of x. 1/y simplifies to 2^n/y. The remainder will be discarded.

Regarding implementation details, you should look for the Xilinx divider core generator and public sequential divider codes.

 

[dipin]

If you want to get x/y as a fractional number, you'll do an integer calculation 2^n*x/y, in other words append n zeros to the right of x. 1/y simplifies to 2^n/y. The remainder will be discarded.

THANKS FVM,
but if i do same to a perfect division (eg: 6/3) it will give result only 1.999...
i tried to increase the scaling factor but still same(1.9999999..) ,is there any other methode to do it,,,
i know it is because of we are avoiding the remainder of (1/3)....so what should we do,,,,.thats why any way to represent the fractional value.. what shuld i do to overcome this.....
thanks & regards

 

[FvM]

There will be rounding errors...
Saying you have 1.999 instead of 2.0 is just a matter of how to read the numbers. But where do you see 1.999...? Without knowing the actual numbers involved in your calculation we can only guess.

 

[dipin]

if i do 2^n*(1/y) and the multplying with x. and later scaling it back. for fraction it is good but for integers say 6/3 this method giving 1.999
...
first scale by 8 256/3 gives 85 1010101 and we are avoiding remainder..
then multiply with 6 1111111110 and again result scaling back 1.111111110 which give 1.9999(approx)

thanks & regards

 

[FvM]

Don't expect 10 bit accuracy with just 8 fractional bits.

You can use more fractional bits if necessary. If you want for some reason an exact integer result, perform a final rounding,