Divider frequency limitations

[RFCMOS]

I've heard that it's quite difficult to design a charge pump PLL at 2GHZ with VCO working at 10GHz in BICMOS process because of divider limitations at these frequencies. Could someone explain what are the physical limitations?
Thanks.

RFCMOS

 

[alanphydenics]

In RF frequency devider, typical BiCMOS, which has 120G FT, the static devider may be can achieve 10~30GHz, but as we known, PLL needs prescaler not static frequency devider, which can perform dual modula deviding, can perform channel selection. This prescaler need more blocks and has a frequency limitation. Also the high the frequency, the more the power. To trade off the power, we have to slow down the frequency. There are some phase switch structure prescaler which can reaches more higher frequency. Thanks.

 

[kjjian]

I think some like "injecting locked divider" can work at 10GHz or ultra.