# Divider for synthesis

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#### Edward_2288

##### Member level 4 dw divider

hi,
I encounter a problem in synthesising a divider to a gate level. for simulation, it can be simply done by using "/" symbol. however during synthesis, an error occurs.

well, anybody know how to synthesis division, let say by 3, 5, 7, etc, please advise me.

thx

#### niuniu

##### Member level 5 serial divider verilog

DC can not synthesize divider, you have to write your own implemenations. find some 'computer arithmatic' book on this topic.

#### Edward_2288

##### Member level 4 combinatorial integer divider verilog

anyone has the e-book or paper? actually, how many ways are they to build a divider?

#### kctang

##### Member level 1 divider verilog code with remainder

What are your requirements(speed, area, latency)?
Pure combinational, or digit-serial divider?

#### Edward_2288

##### Member level 4 divider with quotient and remainder

hi can u show me both ways? thx

#### kctang

##### Member level 1 Hi,

The following combinatorial divider code is written by me when I was a undergraduate and it should be synthesisble. In fact the concept for digit-serial divider is the same excepted that "temp_remainder" is evaluated in each clock cycle.

Another higher radix division requires a lookup table first and you can find the theory in most computer arithematics books, enjoy!!

/**************************************/
module divider(quotient, remainder, dividend, divider);

output [15:0] quotient, remainder;
input [15:0] dividend, divider;

reg [15:0] quotient, remainder;
reg [31:0] scaled_divider, temp_remainder, temp_result;
integer i;

always @(dividend or divider) begin
scaled_divider = {1'b0, divider, 15'h0000};
temp_remainder = {16'h0000, dividend};

for(i = 0;i < 16; i = i + 1) begin
temp_result = temp_remainder - scaled_divider;

if(temp_result[31 - i]) begin // Negative result, Quotient set to '0'
quotient[15 - i] = 1'b0;
end
else begin // Positive result, Quotient set to '1'
quotient[15 - i] = 1'b1;
temp_remainder = temp_result;
end

scaled_divider = scaled_divider >> 1;
end

remainder = temp_remainder[15:0];
end

endmodule
/**************************************/

#### jimjim2k Hi

for a collection of HDL codes for

check each of them with HDL lint tools for synthesizabiliy too.

1. h**p://ntu.csie.org/~b88047/p1/
2. h**p://ntu.csie.org/~b88047/p2/

* -> t

tnx

#### Edward_2288

##### Member level 4 btw, what is the difference between pure combinational and digit-serial divider? is it the number of cycles required to complete a division? thx

#### seasonyangd

##### Member level 3 Edward_2288 said:
anyone has the e-book or paper? actually, how many ways are they to build a divider?

Here is a paper on this topic?

It is a SNUG paper about divider implementation using verilog.

#### Edward_2288

##### Member level 4 kctang said:
Hi,

The following combinatorial divider code is written by me when I was a undergraduate and it should be synthesisble. In fact the concept for digit-serial divider is the same excepted that "temp_remainder" is evaluated in each clock cycle.

Another higher radix division requires a lookup table first and you can find the theory in most computer arithematics books, enjoy!!

/**************************************/
module divider(quotient, remainder, dividend, divider);

output [15:0] quotient, remainder;
input [15:0] dividend, divider;

reg [15:0] quotient, remainder;
reg [31:0] scaled_divider, temp_remainder, temp_result;
integer i;

always @(dividend or divider) begin
scaled_divider = {1'b0, divider, 15'h0000};
temp_remainder = {16'h0000, dividend};

for(i = 0;i < 16; i = i + 1) begin
temp_result = temp_remainder - scaled_divider;

if(temp_result[31 - i]) begin // Negative result, Quotient set to '0'
quotient[15 - i] = 1'b0;
end
else begin // Positive result, Quotient set to '1'
quotient[15 - i] = 1'b1;
temp_remainder = temp_result;
end

scaled_divider = scaled_divider >> 1;
end

remainder = temp_remainder[15:0];
end

endmodule
/**************************************/

Hi...this code will be synthesized into what? how many counters? how many adders? substractors? thx

#### kctang

##### Member level 1 This is a 16bit by 16bit, unsigned combinatinoal divider with no counters. It should have 16 subtractors of various width(max 32).

#### Edward_2288

##### Member level 4 so it means that in one clk cycle, we get the result of division. am i rite?

#### xwcwc1234

##### Full Member level 5 Any one knows where can get a synthesizable Verilog code for digital filter ?

#### kctang

##### Member level 1 Yeap, it gets the result in a single cycle. But it is slow due to cascaded subtractors.

#### taotaocui

##### Newbie level 6 Maybe you can use DW divider in DC during ASIC implementation or Coregen or MegaFunction in FPGA.
It's no a good method that you write everything you need yourself.

#### Edward_2288

##### Member level 4 what is DW divider?

#### heartfree Edward_2288 said:
what is DW divider?
DW -----Design Ware
this is a kind of IP provied by Synopsys.
If you are licensed, you can make a reference when RTL coding.

#### kinjal_book

##### Junior Member level 3 i have got quotient and remainder but i need to combine them to get the floating number

is there any good algorithm

#### posedge

##### Newbie level 1 kinjal_book said:
i have got quotient and remainder but i need to combine them to get the floating number

is there any good algorithm

Two years after original Topic was discusssed ?
It will be more effective for you if you open your own new topic on the subject:

"Synthesizable RTL Floating Point Dividers"

• waleed_1972

Points: 2