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divider bug in Vaucher Truly Modular Programmable Dividers

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louis.chuang

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a family of low-power truly modular

Dear all
when I use the programmable divider from the paper "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology", I found there is a limitaion that paper don't mention.
Though the division ratio extension is sloved, but if the sigma-delta modulator change the division ratio from 2^n to (2^n-1), the division ratio will have error. For example, when sigma-delta modulation change the division between 16 & 15 (control bit will change betwen 0010000 & 0001111), the real division ratio may not be 16 & 15.
Does anyone found this bug, or is there any other method could solve it??
Thank you very much.
 

modular programmable dividers

There will be one clock latency as such when going from low to high., but not from high to low in this divider. There a few techniques to solve this. What was your method
 

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