module divider(
// Outputs
output_clk,
// Inputs
clk, reset_n, divide
);
input clk, reset_n;
output output_clk;
input [7:0] divide;
reg output_clk;
reg [7:0] counter;
wire ld = (divide[0]) ? ((output_clk) ? (counter == 1) : (counter == 0))
: (counter == 1);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
output_clk <= 1'b0;
end else begin
if (ld) begin
output_clk <= ~output_clk ;
counter <= {1'b0,divide[7:1]};
end else
counter <= counter - 1;
end
end
endmodule // divider
module test();
reg clk;
reg [7:0] divide;
reg reset_n;
wire output_clk;
divider divider(
// Outputs
.output_clk (output_clk),
// Inputs
.clk (clk),
.reset_n (reset_n),
.divide (divide[7:0]));
initial begin
$dumpfile("wave.vcd");
$dumpvars();
clk = 0; reset_n = 0; divide = 5;
#33 reset_n = 1;
#500 divide = 10
#500 divide = 9;
#500 divide = 11;
#500 divide = 4;
#500 $finish;
end
always #5 clk = ~clk;
endmodule // test