divide by 5 counter design

[amira]

divide by 5 counter

Hello,

I need to design a divide by 5 counter . My question is , if I design a 3 stage ripple counter , will that be a divide by 5 counter?

Thanks

 

[Iouri]

divide by 5

no. You might need to think about the state machine, also keep in mind you will need at least two processor and second process needs to be active at the negative edge of clock (assuming first process gets active at the rising edge of clokc)


god lack

 

[amira]

mod 5 counter design

thanks for your reply.What do you mean by 2 processes? 2 filp flops? How many flip flops do I need for divide by 5? 2 or 3?

Can anyone please give me some links from where I will get the ideas of the divide by 5 counter. I need to refresh the concept.

Please help.

 

[ankit12345]

how to design modulus-5 counter

There r about 6 solution i derived long back for this type ok ckt.We can use nagative and positve edges in two prosess and design.we can use clk states and a process.Propagate the derived clk to half cycle...etc

 

[amira]

divide-by-5 counter

Hello ankit12345,

can anyone please give me the schemetic for the divide by 5 counter by using t filp flops. Please help. I really need to understand the concept first.

Thanks

 

[keano]

divide-by-5

Hi,

What's a "divide by 5 counter"? Is it a divider?
Please explain to me its behaviour.

Thanks

 

[mpkp123]

divide by five counter

It means deviding the clock by 5.
Well it is not possible to design it simply using three flip flops some other circuitary also needed to go for the negative phase also.

 

[s0shinde]

binary counter divide by 5

Hello Almira,
I have attached a word document explaining the divide by 5 counter design. For more clearity, you can also refer to the link:

**broken link removed**

 

[nand_gates]

designing a divide by 5 counter

Here goes the code for divide by 5 using t_ffs.
Hope this helps!

module div5 (
   // Outputs
   clk_by_5, 
   // Inputs
   clk, reset_n
   );
input clk;
input reset_n;
output clk_by_5;
wire q0, q1, q2, q_n0, q_n1, q_n2;
wire t0 = q_n2; 
wire t1 = q0;
wire t2 = (q0 & q1)| q2;

   assign clk_by_5 = q1;
   t_ff t_ff0(clk, reset_n, t0, q0, q_n0);
   t_ff t_ff1(clk, reset_n, t1, q1, q_n1);
   t_ff t_ff2(clk, reset_n, t2, q2, q_n2);
   
endmodule

module t_ff(clk, reset_n, t, q, q_n);
   input clk, reset_n, t;
   output q, q_n;
   reg    q, q_n;
   
   always @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
         q <= 0;
         q_n <= 1;
      end else begin
         if (t) begin
            q <= ~q;
            q_n <= ~q_n;
         end		
      end
   end	
endmodule

 

[nand_gates]

divide by 5

Here goes the simple testbench.

module test();
   reg  clk; 
   reg  reset_n;
   wire clk_by_5;
   
div5 div5 (
           // Outputs
           .clk_by_5                    (clk_by_5),
           // Inputs
           .clk                         (clk),
           .reset_n                     (reset_n));
initial begin
   $monitor ($time,,"clk = %b reset_n = %b clk_by_5 = %b count = %d", clk, reset_n, clk_by_5, {div5.q2, div5.q1, div5.q0});
   $dumpfile("wave.vcd");
   $dumpvars();
//    $shm_open("./WAVEFORM");
//    $shm_probe(test, "AS");
    clk = 0; reset_n = 0;
    #33 reset_n = 1;
    #1000 $finish;	
end
always #5 clk = ~clk;
endmodule

Here is how I designed it
we need to divide clk by 5 so
we need a mod 5 counter which
counts from 0 to 4. We are going to
use T-ffs to build the counter. We note
that T-ff output toggles whenever t input
is high.

+-----+----------+----------+
|     | curent   |  to get  |
|     |          |  next    |
|     | state    |  state   |
+-----+----------+----------+
|count| q2 q1 q0 | t2 t1 t0 |
+-----+----------+----------+
|  0  | 0  0  0  | 0  0  1  | // Here q0 changes from 0 to 1 hence t0 should be 1.
|  1  | 0  0  1  | 0  1  1  | // Here q1 and q0 changes from 0->1, 1->0 respectively  
|  2  | 0  1  0  | 0  0  1  | // and so on
|  3  | 0  1  1  | 1  1  1  |
|  4  | 1  0  0  | 1  0  0  |
|  0  | 0  0  0  |          |
+-----+----------+----------+

From the table above we see that
t0 = ~q2
t1 = q0
and t2 = (q1 & q0) | q2

Also q2 or q1 can be used as divide by 5
clk output!