Divide by 3 or Divide by n Counter

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divide by n counter

Hi all,
I want to know how to design a divide by 3 counter with 50% duty cycle.
Ramana
 

divide-by-n counter

1. simply use a 2 bit synchronous johnson counter with truth table as 00/01/11....( initial as 11 / Q1, Q0 / Q0 as LSB )
2. a independent T-FF whose clock come from CK*Q1*Q0 + /CK*/Q1*Q0, the output of T-FF is required
3. If full synchronous is required, more complex one similar as about
 

divide by 3 frequency divider

Hi,
Use DCM module which I know is in Xilinx.
BRMadhukar
 

divide by 3 counter

Design a counter asynchromous will be easier using 2 JK flip flops
Use 2 JK flip flops Use the out put of LSB and MSB through a nand gate to trigger the clear pin of the flip flops to restart counting
 

synchronous divide by 10 counter

try this
 
design of divide by 3 counter

just go through this!!!
all the best
 
what is a divide by n counter

I'll try 2 sum up the steps:
1. Generate two clocks at half the desired frequency with a quadrature-phase relationship (constant 90° phase difference between the two clocks).
2. Generate the output frequency by exclusive-ORing the two waveforms together. 'coz of the constant 90° phase offset, only one transition occurs at a time on the input of the exclusive-OR gate.

Reference taken from the file attached...
It gives description of majority type of clock dividers..

Hope it helps u...

tut..
 

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  • clock_dividers_made_easy.pdf
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design a divide-by-7 counter

my design[/img]
 

divide by 3 design

Try to use a divide-by-two frequency divider to generate a signal with half the frequency of the original. And then use an AND Gate to sum up the original and the divided signal.
 

n counter

Use a 3bit counter
 

Re: design of divide by 3 counter

silver_kiss said:
just go through this!!!
all the best
Click to expand...

Good Document Thanks
 

Re: divide by 3 design

yeechyan said:
Try to use a divide-by-two frequency divider to generate a signal with half the frequency of the original. And then use an AND Gate to sum up the original and the divided signal.
Click to expand...

That will give a divide by 2 with 33.33% duty cycle.
 
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Re: divide by 3 design

Use 2 D-FFs, say D1 and D2. both operate on same CLK. And D2=Q1. D1= (Q1 Nand Q2).
 

Re: divide by 3 design

Double the frequency and divide by 6. Multiplying can be done with a RC circuit and a XOR gate. Divide by 6 with 3 flip-flops and a XOR gate.
This circuit will give a 50% duty cycle.

It can be done with the following circuit.



**broken link removed**
 

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