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| `timescale 1ns / 1ps
module d_ff_gates(d,clk,q,q_bar);
input clk;
input d;
output q, q_bar;
wire n1,n2,n3,q_bar_n,clk1;
wire cn,dn,n4,n5,n6;
// First Latch
not (n1,d);
not (clk1,clk);
nand (n2,d,clk1);
nand (n3,n1,clk1);
nand (dn,q_bar_n,n2);
nand (q_bar_n,dn,n3);
// Second Latch
not (cn,clk1);
not (n4,dn);
nand (n5,dn,cn);
nand (n6,n4,cn);
nand (q,q_bar,n5);
nand (q_bar,q,n6);
endmodule |